> sysinfo->link_pair_num=0x1 > entering ht_optimize_link > pos=0x8a, unfiltered freq_cap=0x8075 > pos=0x8a, filtered freq_cap=0x75 > pos=0xd2, unfiltered freq_cap=0x65 > pos=0xd2, filtered freq_cap=0x65 > freq_cap1=0x75, freq_cap2=0x65 > dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 > dev2 old_freq=0x0, freq=0x6, needs_reset=0x1 > width_cap1=0x11, width_cap2=0x11 > dev1 input ln_width1=0x4, ln_width2=0x4 > dev1 input width=0x1 > dev1 output ln_width1=0x4, ln_width2=0x4 > dev1 input|output width=0x11 > old dev1 input|output width=0x11 > dev2 input|output width=0x11 > old dev2 input|output width=0x11 > after ht_optimize_link for link pair 0, reset_needed=0x1 > after optimize_link_read_pointers_chain, reset_needed=0x1 > needs_reset=0x1 > ht reset - > > and it hangs here again. > > I'll try to reduce maximum allowed link frequency and retest.
Same symptoms of incorrect reset code to me. If that's the problem, it will hang as long as there's a reset called. I think it's unlikely that the problem is the link width or frequency if the other board works with the same chips. Thanks, Myles -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
