On 11.12.2008 19:31, Carl-Daniel Hailfinger wrote: > On 11.12.2008 17:49, Stefan Reinauer wrote: > >> Carl-Daniel Hailfinger wrote: >> >> >>> Hi! >>> >>> I'm trying to get coreboot v2 running on my Asus M2A-VM. It is very >>> similar to the AMD DBM690T. It has a 690G/SB600 chipset and an IT8716F >>> SuperIO. >>> >>> My codebase is a slightly modified amd/dbm690t target. I only changed >>> the CPU socket to AM2. >>> >>> coreboot-2.0.0.0-failover Do 11. Dez 01:16:13 CET 2008 starting... >>> bsp_apicid=0x0 >>> core0 started: >>> SBLink=00 >>> NC node|link=00 >>> rs690_early_setup() >>> get_cpu_rev EAX=0x50ff2. >>> CPU Rev is K8_G0. >>> NB Revision is A12. >>> rs690_ht_init k8_ht_freq=0. >>> k8_optimization() >>> rs690_por_init >>> sb600_early_setup() >>> sb600_devices_por_init() >>> sb600_devices_por_init(): SMBus Device, BDF:0-20-0 >>> SMBus controller enabled, sb revision is 0x13 >>> sb600_devices_por_init(): IDE Device, BDF:0-20-1 >>> sb600_devices_por_init(): LPC Device, BDF:0-20-3 >>> sb600_devices_por_init(): P2P Bridge, BDF:0-20-4 >>> sb600_devices_por_init(): SATA Device, BDF:0-18-0 >>> sb600_pmio_por_init() >>> begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202 >>> Current fid_cur: 0x2, fid_max: 0xa >>> Requested fid_new: 0xa >>> FidVid table step fidvid: 0xa >>> end msr fid, vid: hi=0x310a120a, lo=0xa0a020a >>> needs_reset=0x1 >>> ht reset - >>> >>> It hangs after that soft reset. No POST code, nothing else. >>> >>> >>> >> Comment out the FidVid stuff and try again. If that does not help, >> disable link speed changes and try again. >> >> > > Good news. > FidVid is OK. > Coherent HT optimization is OK. > Incoherent HT optimization causes the hang. > > I have added incoherent HT debugging. > > coreboot-2.0.0.0-failover Do 11. Dez 19:20:08 CET 2008 starting... > bsp_apicid=0x0 > Enabling routing table for node 00 done. > Enabling UP settings > Disabling read/write/fill probes for UP... done. > coherent_ht_finalize > done > core0 started: > SBLink=00 > NC node|link=00 > rs690_early_setup() > get_cpu_rev EAX=0x50ff2. > CPU Rev is K8_G0. > NB Revision is A12. > rs690_ht_init k8_ht_freq=0. > k8_optimization() > rs690_por_init > sb600_early_setup() > sb600_devices_por_init() > sb600_devices_por_init(): SMBus Device, BDF:0-20-0 > SMBus controller enabled, sb revision is 0x13 > sb600_devices_por_init(): IDE Device, BDF:0-20-1 > sb600_devices_por_init(): LPC Device, BDF:0-20-3 > sb600_devices_por_init(): P2P Bridge, BDF:0-20-4 > sb600_devices_por_init(): SATA Device, BDF:0-18-0 > sb600_pmio_por_init() > begin msr fid, vid: hi=0x310a1212, lo=0xa0a0202 > Current fid_cur: 0x2, fid_max: 0xa > Requested fid_new: 0xa > FidVid table step fidvid: 0xa > end msr fid, vid: hi=0x310a120a, lo=0xa0a020a > entering optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > entering ht_optimize_link > pos=0x8a, unfiltered freq_cap=0x8075 > pos=0x8a, filtered freq_cap=0x75 > pos=0xd2, unfiltered freq_cap=0x65 > pos=0xd2, filtered freq_cap=0x65 > freq_cap1=0x75, freq_cap2=0x65 > dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 > dev2 old_freq=0x0, freq=0x6, needs_reset=0x1 > width_cap1=0x11, width_cap2=0x11 > dev1 input ln_width1=0x4, ln_width2=0x4 > dev1 input width=0x1 > dev1 output ln_width1=0x4, ln_width2=0x4 > dev1 input|output width=0x11 > old dev1 input|output width=0x11 > dev2 input|output width=0x11 > old dev2 input|output width=0x11 > after ht_optimize_link for link pair 0, reset_needed=0x1 > after optimize_link_read_pointers_chain, reset_needed=0x1 > needs_reset=0x1 > ht reset - > > and it hangs here again. > > I'll try to reduce maximum allowed link frequency and retest. >
It works with 800,400,200 MHz. It fails with 1000 MHz. I didn't test 600 MHz (not supported by RS690G) and 100 MHz. I think I found a bug in RS690 init. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
