ok guys,
a little summary from my side:
i've tried the patch from uwe [1] but there are some issues with the
baud rate and also the same problem as fred [2] had but with a
different output.
the baud problem could be solved with a small workaround: just change
to 57600 in minicom but leave 115200 in the bios source.
uwe wrote then a second patch (see attachment, works with the lastest
svn rev. (remove the old patch before apply the new one)) which fixed
the baud problem and other stuff but not the "poweroff" problem.
my first boot log was:
coreboot-2.0.0.0Fallback Fr 2. Jan 17:10:59 CET 2009 starting...
*sysinfo range: [000cf000,000cf730)
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started:
started ap apicid: 01
SBLink=00
NC node|link=00
begin msr fid, vid 3107121207110202
Current fid_cur: 0x2, fid_max: 0x11
Requested fid_new: 0x11
FidVid table step fidvid: 0xe
200MHZ step fidvid: 0x10
100MHZ step fidvid: 0x11
end msr fid, vid 3107120707110211
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x807f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x1
after optimize_link_read_pointers_chain, reset_needed=0x1
mcp55_num:01
uwe told me to remove all useless hardware during these tests but no difference.
i hope that somebody find a solution to get a working bios for this board.
thats all for now.. i'll keep you up2date if something happens.
[1] http://www.coreboot.org/pipermail/coreboot/2007-October/026410.html
[2] http://thread.gmane.org/gmane.linux.bios/45265/focus=45311
Index: src/mainboard/msi/ms7260/Config.lb
===================================================================
--- src/mainboard/msi/ms7260/Config.lb (Revision 3845)
+++ src/mainboard/msi/ms7260/Config.lb (Arbeitskopie)
@@ -181,47 +181,49 @@
chip southbridge/nvidia/mcp55 # Southbridge
device pci 0.0 on end # HT
device pci 1.0 on # LPC
- chip superio/winbond/w83627ehg # Super I/O
- device pnp 4e.0 on # Floppy
+ chip superio/ite/it8716f # Super I/O
+ device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
- device pnp 4e.1 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 4e.2 on # Com1
+ device pnp 2e.1 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
- device pnp 4e.3 on # Com2 / IrDA
+ device pnp 2e.2 on # Com2 / IrDA
io 0x60 = 0x2f8
irq 0x70 = 3
end
- device pnp 4e.5 on # PS/2 keyboard
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Environment controller
+ io 0x60 = 0x290
+ end
+ device pnp 2e.5 on # PS/2 keyboard
io 0x60 = 0x60
io 0x62 = 0x64
- irq 0x70 = 1 # PS/2 keyboard IRQ
- irq 0x72 = 12 # PS/2 mouse IRQ
+ irq 0x70 = 1
end
- device pnp 4e.6 off # Serial flash interface
- # io 0x62 = 0x100
+ device pnp 2e.6 on # PS/2 mouse
+ irq 0x70 = 12
end
- device pnp 4e.7 off # GPIO1/6, game port, MIDI port
- # io 0x60 = 0x220 # Datasheet: 0x201
- # io 0x62 = 0x300 # Datasheet: 0x330
- # irq 0x70 = 9
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x0008 # TODO: Check if this works!
end
- device pnp 4e.8 off # WDTO#, PLED
+ device pnp 2e.8 on # MIDI
+ io 0x60 = 0x300 # TODO: Check if this works!
+ irq 0x70 = 10
end
- device pnp 4e.9 off # GPIO2/3/4/5, SUSLED
+ device pnp 2e.9 on # Game port
+ io 0x60 = 0x201 # TODO: Check if this works!
end
- device pnp 4e.a off # ACPI
+ device pnp 2e.a on # Consumer IR
+ io 0x60 = 0x310 # TODO: Check if this works!
+ irq 0x70 = 11
end
- device pnp 4e.b on # HWM (for lm-sensors)
- io 0x60 = 0xa10
- end
end
end
device pci 1.1 on # SM 0
@@ -283,15 +285,15 @@
device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1
- device pci 5.2 off end # SATA 2 (N/A on this board)
+ device pci 5.2 on end # SATA 2 (TODO: available?)
device pci 6.0 on end # PCI
device pci 6.1 on end # AZA (HD Audio)
device pci 8.0 on end # NIC
- device pci 9.0 off end # NIC (N/A on this board)
- device pci a.0 off end # PCI E 5 (N/A on this board?)
- device pci b.0 on end # PCI E 4
- device pci c.0 on end # PCI E 3
- device pci d.0 on end # PCI E 2
+ device pci 9.0 on end # NIC (TODO: available?)
+ # device pci a.0 on end # PCI E 5 (TODO: available?)
+ # device pci b.0 on end # PCI E 4 (TODO: available?)
+ # device pci c.0 on end # PCI E 3 (TODO: available?)
+ # device pci d.0 on end # PCI E 2 (TODO: available?)
device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0
register "ide0_enable" = "1"
Index: src/mainboard/msi/ms7260/mptable.c
===================================================================
--- src/mainboard/msi/ms7260/mptable.c (Revision 3845)
+++ src/mainboard/msi/ms7260/mptable.c (Arbeitskopie)
@@ -36,8 +36,8 @@
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
- static const char oem[8] = "MSI ";
- static const char productid[12] = "MS-7260 ";
+ static const char oem[8] = "ASUS ";
+ static const char productid[12] = "M2N-SLI Delu";
struct mp_config_table *mc;
unsigned int sbdn;
int i, j;
Index: src/mainboard/msi/ms7260/Options.lb
===================================================================
--- src/mainboard/msi/ms7260/Options.lb (Revision 3845)
+++ src/mainboard/msi/ms7260/Options.lb (Arbeitskopie)
@@ -166,10 +166,10 @@
default MEM_TRAIN_SEQ = 2
default WAIT_BEFORE_CPUS_INIT = 0
default CONFIG_IOAPIC = 1
-default MAINBOARD_PART_NUMBER = "K9N Neo (MS-7260)"
-default MAINBOARD_VENDOR = "MSI"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260
+default MAINBOARD_PART_NUMBER = "ASUS M2N SLI Deluxe"
+default MAINBOARD_VENDOR = "ASUS"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 # FIXME
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260 # FIXME
default ROM_IMAGE_SIZE = 65536
default STACK_SIZE = 0x2000
default HEAP_SIZE = 0x8000
Index: src/mainboard/msi/ms7260/mainboard.c
===================================================================
--- src/mainboard/msi/ms7260/mainboard.c (Revision 3845)
+++ src/mainboard/msi/ms7260/mainboard.c (Arbeitskopie)
@@ -23,6 +23,6 @@
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_msi_ms7260_ops = {
- CHIP_NAME("MSI K9N Neo (MS-7260) Mainboard")
+ CHIP_NAME("ASUS M2N-SLI Deluxe Mainboard")
};
#endif
Index: src/mainboard/msi/ms7260/cache_as_ram_auto.c
===================================================================
--- src/mainboard/msi/ms7260/cache_as_ram_auto.c (Revision 3845)
+++ src/mainboard/msi/ms7260/cache_as_ram_auto.c (Arbeitskopie)
@@ -78,8 +78,8 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-#include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
+#include "superio/ite/it8716f/it8716f_early_serial.c"
+#include "superio/ite/it8716f/it8716f_early_init.c"
#if USE_FAILOVER_IMAGE == 0
@@ -91,8 +91,7 @@
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
-/* Yes, on the MSI K9N Neo (MS-7260) the Super I/O is at 0x4e! */
-#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
+#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
@@ -244,12 +243,9 @@
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- /* FIXME: This should be part of the Super I/O code/config. */
- pnp_enter_ext_func_mode(SERIAL_DEV);
- /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */
- pnp_write_config(SERIAL_DEV, 0x24, 0);
- w83627ehg_enable_dev(SERIAL_DEV, TTYS0_BASE);
- pnp_exit_ext_func_mode(SERIAL_DEV);
+ it8716f_24mhz_clkin(SERIAL_DEV);
+ it8716f_kill_watchdog(SERIAL_DEV);
+ it8716f_enable_serial(SERIAL_DEV, TTYS0_BASE);
setup_mb_resource_map();
uart_init();
Index: src/superio/ite/it8716f/it8716f_early_init.c
===================================================================
--- src/superio/ite/it8716f/it8716f_early_init.c (Revision 3845)
+++ src/superio/ite/it8716f/it8716f_early_init.c (Arbeitskopie)
@@ -22,17 +22,57 @@
#include <arch/romcc_io.h>
#include "it8716f.h"
+#define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
+#define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number */
+#define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection */
+#define IT8716F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control */
+
+static void it8716f_sio_write(u8 ldn, u8 index, u8 value)
+{
+ outb(IT8716F_CONFIG_REG_LDN, SIO_BASE);
+ outb(ldn, SIO_DATA);
+ outb(index, SIO_BASE);
+ outb(value, SIO_DATA);
+}
+
+static void it8716f_enter_conf(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x01, port);
+ outb(0x55, port);
+ (port == 0x4e) ? outb(0xaa, port) : outb(0x55, port);
+}
+
+static void it8716f_exit_conf(void)
+{
+ it8716f_sio_write(0x00, IT8716F_CONFIG_REG_CC, 0x02);
+}
+
+static void it8716f_24mhz_clkin(device_t dev)
+{
+ it8716f_enter_conf(dev);
+ it8716f_sio_write(0x00, IT8716F_CONFIG_REG_CLOCKSEL, 0x1);
+ it8716f_exit_conf();
+}
+
+static void it8716f_kill_watchdog(device_t dev)
+{
+ it8716f_enter_conf(dev);
+ it8716f_sio_write(0x07, IT8716F_CONFIG_REG_WATCHDOG, 0x00);
+ it8716f_exit_conf();
+}
+
static void it8716f_disable_dev(device_t dev)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
}
-static void it8716f_enable_dev(device_t dev, unsigned iobase)
+static void it8716f_enable_dev(device_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}
-
--
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