Marc,
I have narrowed the reset to the first
msr = rdmsr(0xc0010042);
line in cache_as_ram.c.
I assume the second would do the same thing if it ever made it there.
Booting with the orig bios, linux reports
ts ttp tm stc 100mhzsteps
as the available power options. It is missing fid vid.
Based on the lack of cpuinfo bits and the documentation the says the processor
will do exactly what it is doing, I propose the included patch.
I made the changes to pistachio and norwich also but they are untested.
With this patch I make it here:
coreboot-2.0.0 Wed Jan 7 17:09:38 PST 2009 starting...
bsp_apicid=0x0
Enabling routing table for node 00 done.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
core0 started:
SBLink=00
NC node|link=00
rs690_early_setup()
get_cpu_rev EAX=0x60fc2.
CPU Rev is K8_G0.
NB Revision is A12.
k8_optimization()
rs690_por_init
sb600_early_setup()
sb600_devices_por_init()
sb600_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is 0x13
sb600_devices_por_init(): IDE Device, BDF:0-20-1
sb600_devices_por_init(): LPC Device, BDF:0-20-3
sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
sb600_devices_por_init(): SATA Device, BDF:0-18-0
sb600_pmio_por_init()
Changing FIDVID not supported
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8035
pos=0x8a, filtered freq_cap=0x35
pos=0xd2, unfiltered freq_cap=0x65
pos=0xd2, filtered freq_cap=0x65
freq_cap1=0x35, freq_cap2=0x65
dev1 old_freq=0x5, freq=0x5, needs_reset=0x0
dev2 old_freq=0x5, freq=0x5, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x0
after optimize_link_read_pointers_chain, reset_needed=0x0
rs690_htinit k8_ht_freq=5.
rs690_htinit NB_CFG_Q_F1000_800=0
needs_reset=0x0
sysinfo->nodes: 1 sysinfo->ctrl: cf188 spd_addr: ffffae98
Ram1.00
setting up CPU00 northbridge registers
done.
Ram2.00
Enable 64MuxMode & BurstLength32
Unbuffered
333Mhz
333Mhz
Thanks,
Dan Lykowski
Signed-off-by: Dan Lykowski <[email protected]>
--- On Thu, 1/8/09, Marc Jones <[email protected]> wrote:
From: Marc Jones <[email protected]>
Subject: Re: [coreboot] FIDVID question
To: [email protected]
Cc: "Dan Lykowski" <[email protected]>, "Coreboot"
<[email protected]>
Date: Thursday, January 8, 2009, 12:10 PM
-----Inline Attachment Follows-----
On Thu, Jan 8, 2009 at 1:45 AM, <[email protected]> wrote:
> Hi,
>
> if you check your CPUID, does it support FIDVID?
>
> If yes, then there is another problem. Perhaps you are hit by
> some errata which says first is needed not HT reset (LDTSTOP) but PCI reset.
> I don't have a code at my hand right now, but is HT reset stuff done
> _before_ the fidvid?
>
I think that all the revf/g processors support fidvid even if it can't
be changed. The S1G1 socket means revf and above and checking for
support really isn't needed. I think it is safe for a platform to make
some assumptions like that.
Have you narrowed the reset to the fidvid code? After fidvid setup
there should be a ht reset as Rudolf noted. You can skip fidvid setup
for now. It just means that the processor will run at min frequency.
Marc
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Index: src/mainboard/amd/pistachio/cache_as_ram_auto.c
===================================================================
--- src/mainboard/amd/pistachio/cache_as_ram_auto.c (revision 3850)
+++ src/mainboard/amd/pistachio/cache_as_ram_auto.c (working copy)
@@ -155,6 +155,7 @@
int needs_reset = 0;
u32 bsp_apicid = 0;
msr_t msr;
+ struct cpuid_result cpuid1;
struct sys_info *sysinfo =
(struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE -
DCACHE_RAM_GLOBAL_VAR_SIZE);
@@ -198,17 +199,27 @@
post_code(0x04);
- msr = rdmsr(0xc0010042);
- printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+ /* Check to see if processor is capable of changing FIDVID */
+ /* otherwise it will throw a GP# when reading FIDVID_STATUS */
+ cpuid1 = cpuid(0x80000007);
+ if( (cpuid1.edx & 0x6) == 0x6 ) {
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
+ /* Read FIDVID_STATUS */
+ msr=rdmsr(0xc0010042);
+ printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
- // show final fid and vid
- msr = rdmsr(0xc0010042);
- printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+ enable_fid_change();
+ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+ init_fidvid_bsp(bsp_apicid);
+ /* show final fid and vid */
+ msr=rdmsr(0xc0010042);
+ printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+
+ } else {
+ printk_debug("Changing FIDVID not supported\n");
+ }
+
post_code(0x05);
needs_reset = optimize_link_coherent_ht();
Index: src/mainboard/amd/dbm690t/cache_as_ram_auto.c
===================================================================
--- src/mainboard/amd/dbm690t/cache_as_ram_auto.c (revision 3850)
+++ src/mainboard/amd/dbm690t/cache_as_ram_auto.c (working copy)
@@ -161,6 +161,7 @@
int needs_reset = 0;
u32 bsp_apicid = 0;
msr_t msr;
+ struct cpuid_result cpuid1;
struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
@@ -197,17 +198,27 @@
rs690_early_setup();
sb600_early_setup();
- msr=rdmsr(0xc0010042);
- printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+ /* Check to see if processor is capable of changing FIDVID */
+ /* otherwise it will throw a GP# when reading FIDVID_STATUS */
+ cpuid1 = cpuid(0x80000007);
+ if( (cpuid1.edx & 0x6) == 0x6 ) {
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
+ /* Read FIDVID_STATUS */
+ msr=rdmsr(0xc0010042);
+ printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
- /* show final fid and vid */
- msr=rdmsr(0xc0010042);
- printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+ enable_fid_change();
+ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+ init_fidvid_bsp(bsp_apicid);
+ /* show final fid and vid */
+ msr=rdmsr(0xc0010042);
+ printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+
+ } else {
+ printk_debug("Changing FIDVID not supported\n");
+ }
+
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
rs690_htinit();
Index: src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c (revision 3850)
+++ src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c (working copy)
@@ -259,6 +259,7 @@
int needs_reset; int i;
unsigned bsp_apicid = 0;
+ struct cpuid_result cpuid1;
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -311,8 +312,13 @@
#endif
#if K8_SET_FIDVID == 1
+ /* Check to see if processor is capable of changing FIDVID */
+ /* otherwise it will throw a GP# when reading FIDVID_STATUS */
+ cpuid1 = cpuid(0x80000007);
+ if( (cpuid1.edx & 0x6) == 0x6 ) {
{
+ /* Read FIDVID_STATUS */
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
@@ -332,6 +338,11 @@
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
}
+
+ } else {
+ print_debug("Changing FIDVID not supported\n");
+ }
+
#endif
#if 1
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