Ühel kenal päeval, N, 2009-01-08 kell 18:12, kirjutas Marc Jones: > On Thu, Jan 8, 2009 at 3:45 PM, Myles Watson <[email protected]> wrote: > > > > > >> -----Original Message----- > >> From: Marc Jones [mailto:[email protected]] > >> Sent: Thursday, January 08, 2009 2:16 PM > >> To: Myles Watson; Marc Jones; ron minnich; Coreboot > >> Subject: Re: [coreboot] domain vs device statictree order > >> > >> On Thu, Jan 8, 2009 at 1:17 PM, Ward Vandewege <[email protected]> wrote: > >> > On Thu, Jan 08, 2009 at 01:07:55PM -0700, Myles Watson wrote: > >> >> >> I copied the reserved areas from i440bx_emulation. Like the > >> comments > >> >> >> say, I know these need to be reserved areas, but I'm not exactly > >> sure > >> >> >> where they belong. > >> >> >> > >> >> >> Compile tested. > >> >> >> > >> >> >> Signed-off-by: Myles Watson <[email protected]> > >> >> > > >> >> > There is just a PIC in the Geode so you don't need to reserve the > >> >> > LAPIC range. You do still need to reserve the ROM range. Just fix up > >> >> > the comment. > >> >> > > >> >> > Acked-by: Marc Jones <[email protected]> > >> >> > >> >> Rev 1111. > >> > > >> > Still the same, sadly, cf attached. > >> > > >> > >> I see the graphics device still getting setup even though it has no > >> memory. I think that is might be a problem. This patch hides the > >> header before resource allocation and should avoid the problem and is > >> completely untested..... > > > > It seems cleaner to hide the graphics when there's no memory allocated, but > > is the geodelx always paired with the cs5536? It's surprising to have them > > be that tightly coupled. > > > > I think I'd prefer to hide the device in the cs5536 stage2_fixup. That way > > it can stay in cs5536, but get done in the right order. I would submit a > > patch, but while I was there I saw that there are other things (ide vs nand) > > that probably should be moved at the same time, and Mart's already working > > on that. > > Yes they are that closely attached and use the same SMM code which is > how the device is hidden. I think that hiding the graphics device > during graphics init is the right thing to do.
We now have a graphics device in the device tree of mainboards. How about having a graphics device in northbridge/amd/geodelx or southbridge/amd/cs5536 too, and doing graphics init from there if the device exists in mainboard device tree? Or does that need to be run even on headless? Also, what if we had the possibility to run code for disabled devices - then the vpci hiding could cleanly happen when the device is disabled instead of checks from northbridge code. Like a .disable functor in device_ops? Take it as a possible thought on how to make things more v3-ish if you will. The hiding on zero graphics memory patch is still good in the current state and should be committed for the time being either way imho. Regards, Mart Raudsepp Artec Design LLC -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
