Author: mjones Date: 2009-01-20 01:03:11 +0100 (Tue, 20 Jan 2009) New Revision: 1117
Modified: coreboot-v3/northbridge/via/cn700/pci_domain.c Log: One missed function rename in the stage2 pci resources allocation. phase4_assign_resources is now phase4_set_resources. (trivial) Signed-off-by: Marc Jones <[email protected]> Acked-by: Marc Jones <[email protected]> Modified: coreboot-v3/northbridge/via/cn700/pci_domain.c =================================================================== --- coreboot-v3/northbridge/via/cn700/pci_domain.c 2009-01-15 16:56:44 UTC (rev 1116) +++ coreboot-v3/northbridge/via/cn700/pci_domain.c 2009-01-20 00:03:11 UTC (rev 1117) @@ -114,7 +114,7 @@ /* TODO: shadow ram needs to be controlled via dts */ ram_resource(dev, idx++, 1024, (tolmk - 1024 - (CONFIG_CN700_VIDEO_MB * 1024))); - phase4_assign_resources(&dev->link[0]); + phase4_set_resources(&dev->link[0]); } /** Operations for when the northbridge is running a PCI domain. */ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
