Take BIOS base address into consideration for ICHs.
Signed-off-by: FENG yu ning <[email protected]>
Tested on Intel motherboard D945PLRN by reading.
Current (unpatched) flashrom fails and creates an image file of all null bytes.
Verbose output is attached below. Note the BBAR register, "ich_spi_read_page:
offset=0" and "Transaction error!".
---------- output begins -------------------------------------------------------
$ flashrom -frV -c M25P40 test0
Calibrating delay loop... 492M loops per second, 100 myus = 132 us. OK.
No coreboot table found.
Found chipset "Intel ICH7/ICH7R", enabling flash write...
BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2
tried to set 0xdc to 0x3 on Intel ICH7/ICH7R failed (WARNING ONLY)
Root Complex Register Block address = 0xfed1c000
GCS = 0x464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI)
Top Swap : not enabled
SPIBAR = 0xfed1c000 + 0x3020
0x00: 0x800c (SPIS)
0x02: 0x4040 (SPIC)
0x04: 0x00f80000 (SPIA)
0x08: 0x000000bf (SPID0)
0x0c: 0x00000000 (SPID0+4)
0x10: 0x00000000 (SPID1)
0x14: 0x00000000 (SPID1+4)
0x18: 0xfd61be66 (SPID2)
0x1c: 0x2fe9ffff (SPID2+4)
0x20: 0x000000ff (SPID3)
0x24: 0x00000000 (SPID3+4)
0x28: 0xffff03fb (SPID4)
0x2c: 0x00000010 (SPID4+4)
0x30: 0x00000000 (SPID5)
0x34: 0x00000000 (SPID5+4)
0x38: 0x0be9090f (SPID6)
0x3c: 0x000000ff (SPID6+4)
0x40: 0x00001000 (SPID7)
0x44: 0xffff0000 (SPID7+4)
0x50: 0x00f80000 (BBAR)
0x54: 0x5006 (PREOP)
0x56: 0x123b (OPTYPE)
0x58: 0x05200302 (OPMENU)
0x5c: 0x000100ab (OPMENU+4)
0x60: 0x00000000 (PBR0)
0x64: 0x00000000 (PBR1)
0x68: 0x00000000 (PBR2)
0x6c: 0x00000000 (PBR3)
WARNING: SPI Configuration Lockdown activated.
Generating OPCODES... done
SPI Read Configuration: prefetching disabled, caching enabled, FAILED!
Probing for ST M25P40, 512 KB: Invalid OPCODE 0x9f
No EEPROM/flash device found.
Force read (-f -r -c) requested, forcing chip probe success:
Probing for ST M25P40, 512 KB: Found chip "ST M25P40" (512 KB) at
physical address 0xfff80000.
Force reading flash... ich_spi_read_page: offset=0, number=256, buf=0xb7c2c008
Transaction error!
run OPCODE 0x03 failed
Error readingdone.
---------- output ends
----------------------------------------------------------------------
With the patch applied, flashrom finished without error under the same command.
Hex dump of the image file indicates a successful read.
00000000 0f 5a a5 5a ff ff ff ff ff ff ff ff ff ff ff ff |.Z.Z............|
...
000001a0 ff ff ff ff 49 6e 74 65 6c 20 43 6f 72 70 6f 72 |....Intel Corpor|
000001b0 61 74 69 6f 6e 00 ff ff ff ff ff ff ff ff ff ff |ation...........|
000001c0 ff ff ff ff 44 39 34 35 50 4c 52 4e 00 ff ff ff |....D945PLRN....|
...
0007fff0 0f 09 e9 0b ff 00 00 00 00 10 00 00 00 00 ff ff |................|
Index: flashrom/ichspi.c
===================================================================
--- flashrom/ichspi.c (revision 3869)
+++ flashrom/ichspi.c (working copy)
@@ -66,6 +66,7 @@
#define ICH9_REG_PREOP 0x94 /* 16 Bits */
#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
+#define ICH9_REG_BBAR 0xa0 /* 32 Bits */
// ICH9R SPI commands
#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
@@ -97,6 +98,7 @@
#define ICH7_REG_SPIA 0x04 /* 32 Bits */
#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
+#define ICH7_REG_BBAR 0x50 /* 32 Bits */
#define ICH7_REG_PREOP 0x54 /* 16 Bits */
#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
@@ -375,7 +377,7 @@
{
int write_cmd = 0;
int timeout;
- uint32_t temp32 = 0;
+ uint32_t temp32 = 0, bbar, spia;
uint16_t temp16;
uint32_t a;
uint64_t opmenu;
@@ -387,8 +389,14 @@
write_cmd = 1;
}
- /* Programm Offset in Flash into FADDR */
- REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
+ /* Programm Offset in Flash into SPIA */
+ bbar = REGREAD32(ICH7_REG_BBAR);
+ spia = offset + (bbar & 0x00ffff00);
+ if (offset & 0xff000000 || spia & 0xff000000) {
+ printf_debug("%s: Invalid offset or BBAR. (offset = 0x%08x, BBAR = 0x%08x)\n", __func__, offset, bbar);
+ return 1;
+ }
+ REGWRITE32(ICH7_REG_SPIA, spia);
/* Program data into FDATA0 to N */
if (write_cmd && (datalength != 0)) {
@@ -493,7 +501,7 @@
{
int write_cmd = 0;
int timeout;
- uint32_t temp32;
+ uint32_t temp32, bbar, faddr;
uint32_t a;
uint64_t opmenu;
int opcode_index;
@@ -505,7 +513,13 @@
}
/* Programm Offset in Flash into FADDR */
- REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
+ bbar = REGREAD32(ICH9_REG_BBAR);
+ faddr = offset + (bbar & 0x00ffff00);
+ if (offset & 0xff000000 || faddr & 0xff000000) {
+ printf_debug("%s: Invalid offset or BBAR. (offset = 0x%08x, BBAR = 0x%08x)\n", __func__, offset, bbar);
+ return 1;
+ }
+ REGWRITE32(ICH9_REG_FADDR, faddr);
/* Program data into FDATA0 to N */
if (write_cmd && (datalength != 0)) {
--
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