On 25.01.2009 02:39, Peter Stuge wrote: > Carl-Daniel Hailfinger wrote: > >> (And anyone implementing this should probably add all mails >> explaining the algorithm as code comments. Nobody is going to >> understand such code in a few months if it was written without >> enough comments. ;-) >> > > This is just another allocation algorithm. > > The PCI resource allocation taught us that KISS must be key. >
We have a KISS algorithm for MTRRs right now. It causes >10 minute boots. The RAM init code taught us that good comments are essential and documenting the shortfalls is key. > 6 entries is a sad restriction to deal with. These are times when > >=4GB is not so uncommon. > There are enough common corner cases and restrictions not handled by coreboot. I hope we can get an optimal solution at least for MTRRs. I have a dream. One recent mainstream desktop mainboard that works a least as well as with the alternative. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
