Diff was being silly and I wanted to get the patch posted before I left work
for the day. I've cleaned up the patch and included it.
I wasn't able to find where INTA was used so I used what the RPR lists as
default. INTG. After looking at the mptable, I agree INTA is the correct
answer. I've corrected it. I used dev_find_slot because I copied from the SATA
driver. I've added the comment just like the SATA driver has. I don't know what
the difference is, or why the SATA driver did this.
The reordering was based on what order things happen in the BIOS Developers
guide, RPR, and SATA driver. I fixed the order of the devices that didn't
matter to clean up the change log.
1. Enable the Chip
2. Setup the SMBus registers
3. Setup the Device Registers
4. Look for Codec
5. Init Codec
The codec init was changed to match the description in the RRG pg 235.
Mem Reg: Base + 08h Bit 0. There were unneeded things happening.
So here is the second try.
Thanks,
Dan Lykowski
Signed-off-by: Dan Lykowski <[email protected]>
Index: src/southbridge/amd/sb600/sb600_hda.c
===================================================================
--- src/southbridge/amd/sb600/sb600_hda.c (revision 3921)
+++ src/southbridge/amd/sb600/sb600_hda.c (working copy)
@@ -35,23 +35,27 @@
u32 dword;
int count;
+ /* Write (val & mask) to port */
val &= mask;
dword = readl(port);
dword &= ~mask;
dword |= val;
writel(dword, port);
+ /* Wait for readback of register to
+ * match what was just written to it
+ */
count = 50;
do {
+ /* Wait 1ms based on BKDG wait time */
+ mdelay(1);
dword = readl(port);
dword &= mask;
- udelay(100);
} while ((dword != val) && --count);
+ /* Timeout occured */
if (!count)
return -1;
-
- udelay(540);
return 0;
}
@@ -59,32 +63,28 @@
{
u32 dword;
- /* 1 */
- set_bits(base + 0x08, 1, 1);
+ /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
+ if (set_bits(base + 0x08, 1, 0) == -1)
+ goto no_codec;
- /* 2 */
- dword = readl(base + 0x0e);
- dword |= 7;
- writel(dword, base + 0x0e);
+ /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
+ if (set_bits(base + 0x08, 1, 1) == -1)
+ goto no_codec;
- /* 3 */
- set_bits(base + 0x08, 1, 0);
-
- /* 4 */
- set_bits(base + 0x08, 1, 1);
-
- /* 5 */
+ /* Read in Codec location (BAR + 0xe)[2..0]*/
dword = readl(base + 0xe);
dword &= 7;
-
- /* 6 */
- if (!dword) {
- set_bits(base + 0x08, 1, 0);
- printk_debug("No codec!\n");
- return 0;
- }
+ if (!dword)
+ goto no_codec;
+
return dword;
+no_codec:
+ /* Codec Not found */
+ /* Put HDA back in reset (BAR + 0x8) [0] */
+ set_bits(base + 0x08, 1, 0);
+ printk_debug("No codec!\n");
+ return 0;
}
static u32 cim_verb_data[] = {
@@ -262,26 +262,43 @@
static void hda_init(struct device *dev)
{
+ u8 byte;
+ u32 dword;
u8 *base;
struct resource *res;
u32 codec_mask;
+ device_t sm_dev;
+
+ /* Enable azalia - PM_io 0x59[4], disable ac97 - PM_io 0x59[1..0] */
+ pm_iowrite(0x59, 0xB);
+
+ /* Find the SMBus */
+ /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
+ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- /* SM Setting */
+ /* Set routing pin - SMBus ExtFunc (0xf8/0xfc) */
+ pci_write_config32(sm_dev, 0xf8, 0x00);
+ pci_write_config8(sm_dev, 0xfc, 0xAA);
+ /* Set INTA - SMBus 0x63 [2..0] */
+ byte = pci_read_config8(sm_dev, 0x63);
+ byte &= ~0x7;
+ byte |= 0x0; /* INTA:0x0 - INTH:0x7 */
+ pci_write_config8(sm_dev, 0x63, byte);
- /* Set routing pin */
- pci_write_config32(dev, 0xf8, 0x0);
- pci_write_config8(dev, 0xfc, 0xAA);
- /* Set INTA */
- pci_write_config8(dev, 0x63, 0x0);
- /* Enable azalia, disable ac97 */
- pm_iowrite(0x59, 0xB);
+ /* Program the 2C to 0x437b1002 */
+ dword = 0x437b1002;
+ pci_write_config32(dev, 0x2c, dword);
+ /* Read in BAR */
+ /* Is this right? HDA allows for a 64-bit BAR
+ * but this is only setup for a 32-bit one
+ */
res = find_resource(dev, 0x10);
if (!res)
return;
base = (u8 *) ((u32)res->base);
- printk_debug("base = %08x\n", base);
+ printk_debug("base = %08x\n", (u32)base);
codec_mask = codec_detect(base);
if (codec_mask) {
--
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