Marc Jones wrote: > Setup the MTRRs in stage1 so that memory and cache are available throughout > stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF. > It also sets all system memory to WriteBack cached and sets the ROM > area to cached. > > Signed-off-by: Marc Jones <[email protected]>
Acked-by: Peter Stuge <[email protected]> -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
