On Mon, Feb 9, 2009 at 1:18 PM, Marc Jones <[email protected]> wrote: > On Sat, Feb 7, 2009 at 10:28 AM, Marc Jones <[email protected]> wrote: >> On Sat, Feb 7, 2009 at 4:05 AM, Carl-Daniel Hailfinger >> <[email protected]> wrote: >>> On 06.02.2009 23:37, Marc Jones wrote: >>>> Setup the MTRRs in stage1 so that memory and cache are available throughout >>>> stage2. This fixes problems with VGA graphics ROMs access to >>>> 0xA0000-0xBFFFF. >>>> It also sets all system memory to WriteBack cached and sets the ROM >>>> area to cached. >>>> >>>> Signed-off-by: Marc Jones <[email protected]> > > Fixed the comment for clarity and the ROM size based on the config. > > Marc >
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