On 21.02.2009 0:13 Uhr, ron minnich wrote: > This is a bit updated, and shows how an AP can set POST codes in a > variable visible to the BSP. > > Thanks > > ron > > This patch extends core2 smp support to v3. It is an > adaption of the v2 code, with significant cleanup and > simplification. It also works in CAR mode, and has no .bss or .data > usage. It provides for a way to provide AP POST codes to the BSP. > > It builds and I'll be testing it as soon as I can find the power supply for > the kontron (it got "borrowed"). > Index: arch/x86/intel/core2/init_cpus.c > > new file. Basically an adaptation of the v2 code to v3. All global variables > removed. One big change to note: there is a stack struct, and the > parameters to the secondary_start are struct members. Thus the BSP > can watch the AP, and, neater, the AP can POST to a shared variable > and the BSP can see how far it got. > > Index: arch/x86/secondary.S > .S startup for AP. > Index: arch/x86/Kconfig > Delete a dependency. > Index: northbridge/intel/i945/reset_test.c > Add real cold boot detection. > > Index: mainboard/kontron/986lcd-m/Makefile > Add some new build files. > > Index: mainboard/kontron/986lcd-m/stage1.c > > Get rid of ' in #warning that confused some tool. > > Index: mainboard/kontron/986lcd-m/initram.c > Call init_cpus. > > Index: mainboard/kontron/Kconfig > Turn off SMM for now. > > Index: include/arch/x86/lapic.h > Correct a static inline declaration. > > Signed-off-by: Ronald G. Minnich <[email protected]> >
Acked-by: Stefan Reinauer <[email protected]> -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: [email protected] • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot

