Author: myles Date: 2009-02-27 18:51:16 +0100 (Fri, 27 Feb 2009) New Revision: 3959
Modified: trunk/coreboot-v2/src/cpu/amd/dualcore/dualcore.c trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c Log: This patch makes several CMOS/NVRAM reads dependent on whether there's a table to read. Otherwise you never know what you'll get from the factory BIOS. There are probably more, but these are the ones compiled into the s2895. Signed-off-by: Myles Watson <[email protected]> Acked-by: Peter Stuge <[email protected]> Modified: trunk/coreboot-v2/src/cpu/amd/dualcore/dualcore.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/dualcore/dualcore.c 2009-02-25 08:07:33 UTC (rev 3958) +++ trunk/coreboot-v2/src/cpu/amd/dualcore/dualcore.c 2009-02-27 17:51:16 UTC (rev 3959) @@ -56,9 +56,10 @@ unsigned nodes; unsigned nodeid; - if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // disable dual_core - return; - } + if (HAVE_OPTION_TABLE && + read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { + return; // disable dual_core + } nodes = get_nodes(); Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c 2009-02-25 08:07:33 UTC (rev 3958) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c 2009-02-27 17:51:16 UTC (rev 3959) @@ -72,7 +72,7 @@ nodes = get_nodes(); disable_siblings = !CONFIG_LOGICAL_CPUS; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS == 1 && HAVE_OPTION_TABLE == 1 if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // 0 mean dual core disable_siblings = 1; } Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c 2009-02-25 08:07:33 UTC (rev 3958) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c 2009-02-27 17:51:16 UTC (rev 3959) @@ -1597,7 +1597,8 @@ #if CONFIG_LOGICAL_CPUS==1 unsigned total_cpus; - if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */ + if ((!HAVE_OPTION_TABLE) || + read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */ total_cpus = verify_dualcore(nodes); } else { Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2009-02-25 08:07:33 UTC (rev 3958) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2009-02-27 17:51:16 UTC (rev 3959) @@ -598,11 +598,11 @@ if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; } - if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { + if (HAVE_OPTION_TABLE && + read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { dcl &= ~DCL_DimmEccEn; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); - } static int is_dual_channel(const struct mem_controller *ctrl) @@ -1146,7 +1146,8 @@ { unsigned long tom_k, base_k; - if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { + if ((!HAVE_OPTION_TABLE) || + read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { tom_k = interleave_chip_selects(ctrl); } else { print_debug("Interleaving disabled\r\n"); @@ -1450,7 +1451,7 @@ min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; bios_cycle_time = min_cycle_times[ read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { + if (HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) { min_cycle_time = bios_cycle_time; } min_latency = 2; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
