Hi,
0xcd6/cd7 are the Power Management registers of the Southbridge (BCM5785).
Actually this is very similar to the way the IBM x3455 is handled in 
board_enable.c.

I attached a somewhat improved patch including comments and subsytem id.
If anybody knows how to do all this more elegantly, that would be great.

Regards,
Mondrian


-- 
 Dr. Mondrian Nuessle
 Phone: +49 621 181 2717          University of Heidelberg
 Fax:   +49 621 181 2713          Computer Architecture Group
 mailto:[email protected]         http://ra.ziti.uni-heidelberg.de
Add support for HP DL145 G3.
This is a BCM5785 based machine, WP# and TLB# need to be deasserted
using GPIO 0 and 2 from the PM registers of the southbridge.
This is very similar to the x3455 implementation.

Signed-off-by: Mondrian nuessle <[email protected]>

Index: flashrom/board_enable.c
===================================================================
--- flashrom/board_enable.c	(revision 4030)
+++ flashrom/board_enable.c	(working copy)
@@ -329,6 +329,21 @@
 	return 0;
 }
 
+static int board_hp_dl145_g3_enable(const char *name)
+{
+	uint8_t byte;
+
+	/* Set GPIO lines in the Broadcom HT-1000 southbridge. */
+	OUTB(0x44, 0x0cd6);    //select GPIO 0 reg from PM regs
+	byte = INB(0x0cd7);
+	/* set GPIOs 2 and 3 to 1, 
+	   these are connected to WP# and TLB# of the flash device */
+	OUTB(byte  | 0x24, 0x0cd7); 
+
+	return 0;
+}
+
+
 /**
  * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards.
  */
@@ -859,6 +874,21 @@
 		.enable			= board_ibm_x3455,
 	},
 	{
+		.first_vendor = 0x1166,
+		.first_device = 0x0205,
+		.first_card_vendor = 0x1166,
+		.first_card_device = 0x0201,
+		.second_vendor = 0x0000,
+		.second_device = 0x0000,
+		.second_card_vendor = 0x0000,
+		.second_card_device = 0x0000,
+		.lb_vendor = "hp",
+		.lb_part = "dl145_g3",
+		.name = "HP DL145 G3",
+		.enable = board_hp_dl145_g3_enable,
+	},
+
+	{
 		.first_vendor		= 0x8086,
 		.first_device		= 0x7110,
 		.first_card_vendor	= 0x0000,
-- 
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot

Reply via email to