Hello Peter,
   I applied the patch that u had sent, but still its not working.

Here's the output:
{-------------------------------
# ./flashrom -m "portwell:ppap-2020vl" -E

Calibrating delay loop... OK.
No coreboot table found.
Found chipset "VIA VT8237", enabling flash write... OK.

Unknown vendor:board from coreboot table or -m option: portwell:ppap-2020vl

Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000.
Erasing flash chip... ERASE FAILED!
FAILED!
ERROR at 0x00000000: Expected=0xff, Read=0x49
--------------------------------}

I looked at the code and found that in "board_flash_enable" routine, "board_match_coreboot_name" fails in "pci_dev_find", and so board is returned as NULL.

Please find the attached output of lspci -vnn.

Please guide me further!

Rgds,
Vinod
stress:/tmp # lspci -i ./pci.ids -vnn
0000:00:00.0 Class 0600: 1106:0314
        Subsystem: 1106:0314
        Flags: bus master, 66Mhz, medium devsel, latency 8
        Memory at e8000000 (32-bit, prefetchable)
        Capabilities: [80] AGP version 3.5
        Capabilities: [50] Power Management version 2

0000:00:00.1 Class 0600: 1106:1314
        Flags: bus master, medium devsel, latency 0

0000:00:00.2 Class 0600: 1106:2314
        Flags: bus master, medium devsel, latency 0

0000:00:00.3 Class 0600: 1106:3208
        Flags: bus master, medium devsel, latency 0

0000:00:00.4 Class 0600: 1106:4314
        Flags: bus master, medium devsel, latency 0

0000:00:00.7 Class 0600: 1106:7314
        Flags: bus master, medium devsel, latency 0

0000:00:01.0 Class 0604: 1106:b198
        Flags: bus master, 66Mhz, medium devsel, latency 0
        Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
        Memory behind bridge: f4000000-f5ffffff
        Prefetchable memory behind bridge: f0000000-f3ffffff
        Secondary status: SERR
        Capabilities: [70] Power Management version 2

0000:00:08.0 Class 0200: 10ec:8139 (rev 10)
        Subsystem: 10ec:8139
        Flags: bus master, medium devsel, latency 32, IRQ 10
        I/O ports at d000
        Memory at f6000000 (32-bit, non-prefetchable) [size=256]
        Capabilities: [50] Power Management version 2

0000:00:09.0 Class 0200: 10ec:8139 (rev 10)
        Subsystem: 10ec:8139
        Flags: bus master, medium devsel, latency 32, IRQ 11
        I/O ports at d400
        Memory at f6001000 (32-bit, non-prefetchable) [size=256]
        Capabilities: [50] Power Management version 2

0000:00:0a.0 Class 0200: 10ec:8139 (rev 10)
        Subsystem: 10ec:8139
        Flags: bus master, medium devsel, latency 32, IRQ 7
        I/O ports at d800
        Memory at f6002000 (32-bit, non-prefetchable) [size=256]
        Capabilities: [50] Power Management version 2

0000:00:0b.0 Class 0200: 10ec:8139 (rev 10)
        Subsystem: 10ec:8139
        Flags: bus master, medium devsel, latency 32, IRQ 5
        I/O ports at dc00
        Memory at f6003000 (32-bit, non-prefetchable) [size=256]
        Capabilities: [50] Power Management version 2

0000:00:0f.0 Class 0101: 1106:3149 (rev 80) (prog-if 8f [Master SecP SecO PriP 
PriO])
        Subsystem: 1106:3149
        Flags: bus master, medium devsel, latency 32, IRQ 11
        I/O ports at e800
        I/O ports at e400 [size=4]
        I/O ports at e500 [size=8]
        I/O ports at e600 [size=4]
        I/O ports at e700 [size=16]
        I/O ports at e000 [size=256]
        Capabilities: [c0] Power Management version 2

0000:00:0f.1 Class 0101: 1106:0571 (rev 06) (prog-if 8a [Master SecP PriP])
        Subsystem: 1106:0571
        Flags: bus master, medium devsel, latency 32, IRQ 10
        I/O ports at e900 [size=16]
        Capabilities: [c0] Power Management version 2

0000:00:10.0 Class 0c03: 1106:3038 (rev 81)
        Subsystem: 1106:3038
        Flags: bus master, medium devsel, latency 32, IRQ 10
        I/O ports at ea00 [size=32]
        Capabilities: [80] Power Management version 2

0000:00:10.1 Class 0c03: 1106:3038 (rev 81)
        Subsystem: 1106:3038
        Flags: bus master, medium devsel, latency 32, IRQ 10
        I/O ports at eb00 [size=32]
        Capabilities: [80] Power Management version 2

0000:00:10.2 Class 0c03: 1106:3038 (rev 81)
        Subsystem: 1106:3038
        Flags: bus master, medium devsel, latency 32, IRQ 11
        I/O ports at ec00 [size=32]
        Capabilities: [80] Power Management version 2

0000:00:10.3 Class 0c03: 1106:3038 (rev 81)
        Subsystem: 1106:3038
        Flags: bus master, medium devsel, latency 32, IRQ 11
        I/O ports at ed00 [size=32]
        Capabilities: [80] Power Management version 2

0000:00:10.4 Class 0c03: 1106:3104 (rev 86) (prog-if 20)
        Subsystem: 1106:3104
        Flags: bus master, medium devsel, latency 32, IRQ 7
        Memory at f6004000 (32-bit, non-prefetchable)
        Capabilities: [80] Power Management version 2

0000:00:11.0 Class 0601: 1106:3227
        Subsystem: 1106:3227
        Flags: bus master, stepping, medium devsel, latency 0
        Capabilities: [c0] Power Management version 2

0000:01:00.0 Class 0300: 1106:3344 (rev 01)
        Subsystem: 1106:3344
        Flags: bus master, 66Mhz, medium devsel, latency 32, IRQ 10
        Memory at f0000000 (32-bit, prefetchable) [size=f5000000]
        Memory at f4000000 (32-bit, non-prefetchable) [size=16M]
        Expansion ROM at 00010000 [disabled]
        Capabilities: [60] Power Management version 2
        Capabilities: [70] AGP version 3.0
-- 
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot

Reply via email to