So, after trying to figure out some stuff, and getting helped in some cases, here is the next result.
This Fix patches some incorrect things in mptable.c and includes the first patch as well. The difference now is, that PCI-E graphics work well without ACPI support (which is in work for that board.) Last time the PCI-E card worked here because i used my source tree with acpi- support and not a plain v2 tree. In that acpi-tree there was the original bios dsdt.asl, which included the pci routing table. I want to give special thanks to Rudolf Ruik Marek which helped me to figure out the right PCI Routing Table from the vendors dsdt.asl file. *Thanks!* My patch is attached, and works here on the hardware revision 2 of the m57sli. I hope it will work also on v1 and is helpful to others. In the patch there are a few TODO's marked, maybe someone could help to find that out/fix that. (Most of this is checking the configuration again.) Maybe there stay some errors with the interrupt routing on the PCI-E 1x ports, but i can't do that easily because i've no hardware which uses PCI-E 1x. After having that patch verified by others, it should be possible to complete the ACPI-support for the M57SLI in a few hours. Otherwise it would be necessary to get some information of the v1 boards. (dsdt.asl/dsl (use acpidump, iasl), dmesg | grep -i acpi, lspci from linux running the vendors bios.) I hope that this could be done in the next days, and i'm really looking forward to a fully working coreboot support for M57SLI. :)
Index: mptable.c
===================================================================
--- mptable.c (revision 4027)
+++ mptable.c (working copy)
@@ -88,13 +88,13 @@
smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
}
- dword = 0x43c6c643;
+ dword = 0x0030C003; //TODO: Check again and if hw:v1 is the same.
pci_write_config32(dev, 0x7c, dword);
- dword = 0x81001a00;
+ dword = 0x2DA10A09; //TODO: Check again and if hw:v1 is the same.
pci_write_config32(dev, 0x80, dword);
- dword = 0xd0001202;
+ dword = 0x8010D202; //TODO: Check again and if hw:v1 is the same.
pci_write_config32(dev, 0x84, dword);
}
@@ -131,30 +131,26 @@
PCI_INT(0,sbdn+1,1, 10); /* SMBus */
PCI_INT(0,sbdn+2,0, 22); /* USB */
PCI_INT(0,sbdn+2,1, 23); /* USB */
- PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
- PCI_INT(0,sbdn+5,0, 20); /* SATA */
- PCI_INT(0,sbdn+5,1, 23); /* SATA */
- PCI_INT(0,sbdn+5,2, 21); /* SATA */
+ PCI_INT(0,sbdn+6,1, 21); /* HD Audio */
+ PCI_INT(0,sbdn+5,0, 22); /* SATA */
+ PCI_INT(0,sbdn+5,1, 21); /* SATA */
+ PCI_INT(0,sbdn+5,2, 20); /* SATA */
- PCI_INT(0,sbdn+8,0, 22); /* GBit Ether */
+ /* TODO: Check why udev renames eth0 to eth1 at boot time */
+ PCI_INT(0,sbdn+8,0, 22); /* GBit Ether */
+
+ /* TODO: why does the bus nummber increase to 7
+ when using coreboot (proprietary bios bus for
+ pci-e 16x is 2)? */
+ PCI_INT(7,sbdn+0,0, 16); //PCI-E 16x on hw:v2
+
+ PCI_INT(1,sbdn+7,0, 19); /* PCI 1 on hw:v2 */
+ PCI_INT(1,sbdn+8,0, 16); /* PCI 2 on hw:v2 */
- /* The PCIe slots, each on its own bus */
- for(j=7; j>=2; j--) {
- if(!bus_mcp55[j]) continue;
- for(i=0;i<4;i++) { /* map all functions */
- PCI_INT(j,0,i, 16+(1+j+i)%4);
- }
- }
-
- /* On bus 1: the physical PCI bus slots... */
- for(j=0; j<2; j++) /* on a Rev 1.x board, they are devs 7 and 8 */
- for(i=0;i<4;i++) { /* map all functions */
- PCI_INT(1,7+j,i, 16+(3+i+j)%4);
- }
/* ... and OB FireWire */
PCI_INT(1,0x0a,0, 18);
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
Index: cache_as_ram_auto.c
===================================================================
--- cache_as_ram_auto.c (revision 4027)
+++ cache_as_ram_auto.c (working copy)
@@ -137,10 +137,10 @@
#define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0xA8,/* GPIO40 PCI_GNT2 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0xA8,/* GPIO41 PCI_REQ2 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x48,/* GPIP60 FANCTL0 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x48,/* GPIO61 FANCTL1 */
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
interrupt_fix_second_try.patch.gpg
Description: application/pgp-encrypted
signature.asc
Description: This is a digitally signed message part.
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