On 04.04.2009 01:06, Joseph Smith wrote: > > On Sat, 04 Apr 2009 00:26:19 +0200, Carl-Daniel Hailfinger > <[email protected]> wrote: > >> [ROMCC->CAR] >> Great. Will a bad reflash hurt you? >> >> > No, as long as it doesn't blow the thing up :-0 >
Heh. That won't happen unless an endless loop is too much for your cooling setup. >> What you need to try this one out: >> - a POST card or another way to fetch POST codes. >> - tell me whether POST works by default or you need special setup. >> - a will to try out v3 with some patches. >> > Ok, I have a PCI/Parallel Post Card. The RM4100 doesn't have eithor, the > IP1000 does have a PCI slot so we can use that for testing. > Good. Can you verify that the PCI POST card works? >> The idea is to test the v3 intel CAR code which has not been on real >> hardware yet, but it is a much cleaner and more readable implementation >> compared to v2. I'm hoping we don't need chipset specific stuff for POST >> to work. >> > Not sure, serial output works fine. > We'll debug very early code, before serial can be set up. >> I need info on the cache size of your processor, though. Unreliable CAR >> is not nearly as much fun as reliable CAR. >> > 512k > > http://processorfinder.intel.com/details.aspx?sSpec=SL68W > Thanks. Can you find out L1 cache sizes as well? The spec page was not clear about that. And is the processor hyperthreading capable? I'll follow up with a patch on Wednesday or Thursday. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
