On Mon, Apr 20, 2009 at 10:17:43AM -0600, Marc Jones wrote: > On Sun, Apr 19, 2009 at 8:38 AM, Kevin O'Connor <[email protected]> wrote: > > Another optimization I could make would be to reduce the 90ms it takes > > to copy the vga rom from flash. Using 4 byte reads instead of 1 byte > > reads will likely help. However, enabling an mtrr for the flash would > > likely lead to the best results. > > We have been discussing this in another thread. The 4byte read will > make the most improvement and the cache only helps a lot if the ROM is > compressed. You are still bound by the width and speed of the ROM > access. LPC/FWH is typically setup to be very slow.
I implemented a 4byte copy on Sunday night - it dropped the copy time from 90ms to 50ms. It's in the latest SeaBIOS git. I was hoping that caching flash would allow the procesor to do cache-line sized reads. But, you have a good point about the LPC/FWH being a limit. Does anyone know if 50ms is the lower limit on reading 63488 bytes from flash? It still seems high. -Kevin -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
