On Tue, Apr 21, 2009 at 04:00:08AM +0200, Peter Stuge wrote: > Kevin O'Connor wrote: > > But, you have a good point about the LPC/FWH being a limit. Does > > anyone know if 50ms is the lower limit on reading 63488 bytes from > > flash? It still seems high. > > Memory Read is the cycle used by LPC chips, 1 byte at a time. > Firmware Memory Read is used by FWH chips, 1/2/4/128 bytes at a time. > Often only 1. > > 1 byte LPC needs 21 LPC clocks, 630 ns * 63488 = 39997440 ns = 40 ms. > 1 byte FWH needs 19 LPC clocks, 570 ns * 63488 = 36188160 ns = 36 ms. > > I think you're as close as you will get without multibyte Firmware > Memory Read: > > 128 byte FWH needs 273 LPC clocks = 8.27 us * (63488/128) = 4.1 ms.
Thanks Peter. I don't think my epia-cn has FWH. With FWH, will a cache-line fill result in a 128byte flash read, or does one have to implement special instructions to make use of it? As a side note, things will also improve a little with lzma compression of the roms. -Kevin -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
