On 05.05.2009 19:59, ron minnich wrote: > On Tue, May 5, 2009 at 10:50 AM, Peter Stuge <[email protected]> wrote: > > >> No sir. >> > > This is great! > > >> None have single byte erase blocks, but most of the SPI flash chips >> can actually do 256 byte erase blocks. >> > > Should we move to 256 byte default alignment? >
256 byte LAR member _content_ alignment or _header_ alignment? Sometimes it may be useful to have the content aligned. >> I keep imagining how I will be able to safely update the coreboot >> normal image but keep fallback, stages and payloads untouched. >> > > me too. > With LAR and a patched flashrom this is possible right now. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
