On 07.05.2009 16:40, Ali Nadalizadeh wrote: > Works on my hardware except that it is very slow, so changing usleep from > 1000 to 10 > and increasing timeout to 100 * 1000 * 60 (line 461 ichspi.c) results in a > fast erase/read (about 2.5 sec) > and successful write in 62 seconds. > > Test Log : > > a...@velocity:~/tmp/f$ sudo time ./flashrom/flashrom -w mybios.rom > flashrom v0.9.0-r471 > Calibrating delay loop... OK. > No coreboot table found. > Found chipset "Intel ICH7M", enabling flash write... OK. > Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. > Flash image seems to be a legacy BIOS. Disabling checks. > 62.14user 0.10system 1:03.08elapsed 98%CPU (0avgtext+0avgdata 0maxresident)k > 0inputs+0outputs (0major+512minor)pagefaults 0swaps > > a...@velocity:~/tmp/f$ sudo time ./flashrom/flashrom -r ddd > flashrom v0.9.0-r471 > Calibrating delay loop... OK. > No coreboot table found. > Found chipset "Intel ICH7M", enabling flash write... OK. > Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. > Reading flash... done. > 2.87user 0.06system 0:03.05elapsed 96%CPU (0avgtext+0avgdata 0maxresident)k > 0inputs+2048outputs (0major+513minor)pagefaults 0swaps > > a...@velocity:~/tmp/f$ diff ddd mybios.rom > > a...@velocity:~/tmp/f$ > > > Regards -- > Ali Nadalizadeh > > On Thu, May 7, 2009 at 5:44 PM, Carl-Daniel Hailfinger wrote: > >> Chips like the SST SST25VF080B can only handle single byte writes >> outside AAI mode. >> >> Change SPI architecture to handle 1-byte chunk chip writing differently >> from 256-byte chunk chip writing. >> >> Convert all flashchips.c entries with SPI programing to the 256-byte >> version by default. >> >> Change the flashchips entry for SST SST25VF080B to 1-byte writing. >> >> Signed-off-by: Carl-Daniel Hailfinger <[email protected]> >>
Self-acked and committed in r485 and r486. I could not leave a killer bug in flashrom any longer. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
