On Thu, May 28, 2009 at 10:15 AM, Stefan Reinauer <[email protected]> wrote: > On 28.05.2009 17:32 Uhr, Myles Watson wrote: >> Remaining issues: >> 1. Right now I'm testing it with a reserved area for the IOAPIC in the >> southbridge and a reserved area in the lpc/ISA function of the southbridge. >> >> The downside of this is that I have to touch every southbridge to add it. I >> think it is the right place, though. >> > Not so much of a downside, since this is a fix for a real issue, and > puts the code where it (in my opinion) belongs. Good. I agree.
>> 2. Kontron will break because I removed its special case from the resource >> allocator. I think with the new resource allocator it will be easy to fix, >> but I'd like a Kontron tester. >> > I'll be glad to test... Can you suggest a fix or give a pointer on how > to fix this? If we can get rid of the PCIe hole handling hack, I'm all > for checking this in. I think there are a couple of possible fixes depending on what the real problem is. If the problem is that it needs to be at a fixed address, allocate it at the top (as high as you can before the IOAPIC) of the address space, and mark it fixed. I guess there are too many other possibilities for why you needed to implement it that way, but I'd be happy to help you solve the problem. Thanks, Myles -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
