Hello, I've given it another try to fix the mptable of the M57SLI.
The attached patch fixes for me the following things:
* Nvidia graphic device works on PCIe-16x slot (black).
* Both PCI cards in the two available slots work fine.
* Also the PCIe 1x slots should work fine. (untested)
It would be fine if someone of you could test and verify if that patch works on
hardware revision v1 too.
I hope that this fixes all the problems along with interrupts for this
mainboard and I'm looking forward that someone can verify/test this.
Kind regards,
Harald
PS: Is it necessary to add PCI_INT for 00:08/07.01-03?
Index: mptable.c
===================================================================
--- mptable.c (revision 4326)
+++ mptable.c (working copy)
@@ -67,7 +67,7 @@
get_bus_conf();
sbdn = sysconf.sbdn;
-/*Bus: Bus ID Type*/
+ /*Bus: Bus ID Type*/
/* define bus and isa numbers */
for(j= 0; j < 256 ; j++) {
if(bus_type[j])
@@ -75,7 +75,7 @@
}
smp_write_bus(mc, bus_isa, "ISA ");
-/*I/O APICs: APIC ID Version State Address*/
+ /*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
@@ -87,14 +87,11 @@
if (res) {
smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
}
-
- dword = 0x43c6c643;
+ dword = 0x0030c606;
pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x81001a00;
+ dword = 0xd1001009;
pci_write_config32(dev, 0x80, dword);
-
- dword = 0xd0001202;
+ dword = 0x20000802;
pci_write_config32(dev, 0x84, dword);
}
@@ -128,33 +125,28 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))
- PCI_INT(0,sbdn+1,1, 10); /* SMBus */
- PCI_INT(0,sbdn+2,0, 22); /* USB */
- PCI_INT(0,sbdn+2,1, 23); /* USB */
- PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
- PCI_INT(0,sbdn+5,0, 20); /* SATA */
- PCI_INT(0,sbdn+5,1, 23); /* SATA */
- PCI_INT(0,sbdn+5,2, 21); /* SATA */
+ PCI_INT(0,sbdn+1,1, 10); /* SMBus */
+ PCI_INT(0,sbdn+2,0, 22); /* USB */
+ PCI_INT(0,sbdn+2,1, 23); /* USB */
+ PCI_INT(0,sbdn+5,0, 21); /* SATA */
+ PCI_INT(0,sbdn+5,1, 23); /* SATA */
+ PCI_INT(0,sbdn+5,2, 22); /* SATA */
+ PCI_INT(0,sbdn+6,1, 21); /* HD Audio */
+ PCI_INT(0,sbdn+8,0, 20); /* GBit Ether */
+ PCI_INT(1,sbdn+0x0a,0, 18); /* FireWire */
+
+ PCI_INT(1,sbdn+7,0, 19); /* PCI #1 (near cpu) */
+ PCI_INT(1,sbdn+8,0, 18); /* PCI #2 (near edge) */
- PCI_INT(0,sbdn+8,0, 22); /* GBit Ether */
-
/* The PCIe slots, each on its own bus */
for(j=7; j>=2; j--) {
if(!bus_mcp55[j]) continue;
- for(i=0;i<4;i++) { /* map all functions */
- PCI_INT(j,0,i, 16+(1+j+i)%4);
- }
+ for(i=0;i<4;i++) { /* map all functions */
+ PCI_INT(j,0,i, 16);
+ }
}
- /* On bus 1: the physical PCI bus slots... */
- for(j=0; j<2; j++) /* on a Rev 1.x board, they are devs 7 and 8 */
- for(i=0;i<4;i++) { /* map all functions */
- PCI_INT(1,7+j,i, 16+(3+i+j)%4);
- }
- /* ... and OB FireWire */
- PCI_INT(1,0x0a,0, 18);
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
Index: Options.lb
===================================================================
--- Options.lb (revision 4326)
+++ Options.lb (working copy)
@@ -87,6 +87,8 @@
uses HW_MEM_HOLE_SIZE_AUTO_INC
uses K8_HT_FREQ_1G_SUPPORT
+uses HAVE_HIGH_TABLES
+
uses HT_CHAIN_UNITID_BASE
uses HT_CHAIN_END_UNITID_BASE
uses SB_HT_CHAIN_ON_BUS0
@@ -169,6 +171,9 @@
##
default HAVE_MP_TABLE=1
+## HIGH tables support
+default HAVE_HIGH_TABLES=1
+
## ACPI tables will be included
default HAVE_ACPI_TABLES=0
Index: cache_as_ram_auto.c
===================================================================
--- cache_as_ram_auto.c (revision 4326)
+++ cache_as_ram_auto.c (working copy)
@@ -134,10 +134,10 @@
#define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0xA8,/* GPIO40 PCI_GNT2 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0xA8,/* GPIO41 PCI_REQ2 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x48,/* GPIP60 FANCTL0 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x48,/* GPIO61 FANCTL1 */
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
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