Author: hailfinger Date: 2009-06-05 19:48:08 +0200 (Fri, 05 Jun 2009) New Revision: 578
Modified: trunk/82802ab.c trunk/am29f040b.c trunk/en29f002a.c trunk/flash.h trunk/flashrom.c trunk/ichspi.c trunk/internal.c trunk/it87spi.c trunk/jedec.c trunk/m29f002.c trunk/m29f400bt.c trunk/mx29f002.c trunk/sharplhf00l04.c trunk/spi.c trunk/sst28sf040.c trunk/stm50flw0x0x.c trunk/udelay.c trunk/w29ee011.c trunk/w39v040c.c trunk/w39v080fa.c trunk/wbsio_spi.c Log: Add external programmer delay functions so external programmers can handle the delay on their own if needed. Signed-off-by: Carl-Daniel Hailfinger <[email protected]> Acked-by: Uwe Hermann <[email protected]> Acked-by: Urja Rannikko <[email protected]> Modified: trunk/82802ab.c =================================================================== --- trunk/82802ab.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/82802ab.c 2009-06-05 17:48:08 UTC (rev 578) @@ -53,9 +53,9 @@ #endif chip_writeb(0xff, bios); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -65,7 +65,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -92,7 +92,7 @@ // put another command to get out of status register mode chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -124,7 +124,7 @@ // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); - myusec_delay(10); + programmer_delay(10); // now let's see what the register is status = wait_82802ab(flash->virtual_memory); //print_82802ab_status(status); Modified: trunk/am29f040b.c =================================================================== --- trunk/am29f040b.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/am29f040b.c 2009-06-05 17:48:08 UTC (rev 578) @@ -29,7 +29,7 @@ chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x30, bios + address); - sleep(2); + programmer_delay(2 * 1000 * 1000); /* wait for Toggle bit ready */ toggle_ready_jedec(bios + address); @@ -75,7 +75,7 @@ chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id) @@ -95,7 +95,7 @@ chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x10, bios + 0x555); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; Modified: trunk/en29f002a.c =================================================================== --- trunk/en29f002a.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/en29f002a.c 2009-06-05 17:48:08 UTC (rev 578) @@ -37,7 +37,7 @@ chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x90, bios + 0x555); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios + 0x100); id2 = chip_readb(bios + 0x101); @@ -70,7 +70,7 @@ chip_writeb(0x55, bios + 0xAAA); chip_writeb(0x90, bios + 0x555); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios + 0x100); id2 = chip_readb(bios + 0x101); @@ -97,7 +97,7 @@ chipaddr dst = bios; //chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); erase_chip_jedec(flash); printf("Programming page: "); Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/flash.h 2009-06-05 17:48:08 UTC (rev 578) @@ -103,6 +103,8 @@ uint8_t (*chip_readb) (const chipaddr addr); uint16_t (*chip_readw) (const chipaddr addr); uint32_t (*chip_readl) (const chipaddr addr); + + void (*delay) (int usecs); }; extern const struct programmer_entry programmer_table[]; @@ -118,6 +120,7 @@ uint8_t chip_readb(const chipaddr addr); uint16_t chip_readw(const chipaddr addr); uint32_t chip_readl(const chipaddr addr); +void programmer_delay(int usecs); #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) @@ -590,7 +593,7 @@ #define W_49V002FA 0x32 /* udelay.c */ -void myusec_delay(int time); +void myusec_delay(int usecs); void myusec_calibrate_delay(void); /* pcidev.c */ @@ -652,6 +655,7 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void internal_delay(int usecs); void *fallback_map(const char *descr, unsigned long phys_addr, size_t len); void fallback_unmap(void *virt_addr, size_t len); void fallback_chip_writew(uint16_t val, chipaddr addr); Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/flashrom.c 2009-06-05 17:48:08 UTC (rev 578) @@ -46,6 +46,7 @@ .chip_writeb = internal_chip_writeb, .chip_writew = internal_chip_writew, .chip_writel = internal_chip_writel, + .delay = internal_delay, }, { @@ -59,6 +60,7 @@ .chip_writeb = dummy_chip_writeb, .chip_writew = dummy_chip_writew, .chip_writel = dummy_chip_writel, + .delay = internal_delay, }, { @@ -72,6 +74,7 @@ .chip_writeb = nic3com_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, + .delay = internal_delay, }, { @@ -85,6 +88,7 @@ .chip_writeb = satasii_chip_writeb, .chip_writew = fallback_chip_writew, .chip_writel = fallback_chip_writel, + .delay = internal_delay, }, { @@ -98,6 +102,7 @@ .chip_writeb = dummy_chip_writeb, .chip_writew = dummy_chip_writew, .chip_writel = dummy_chip_writel, + .delay = internal_delay, }, {}, @@ -155,6 +160,11 @@ return programmer_table[programmer].chip_readl(addr); } +void programmer_delay(int usecs) +{ + programmer_table[programmer].delay(usecs); +} + void map_flash_registers(struct flashchip *flash) { size_t size = flash->total_size * 1024; Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/ichspi.c 2009-06-05 17:48:08 UTC (rev 578) @@ -453,7 +453,7 @@ /* wait for cycle complete */ timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) { - myusec_delay(10); + programmer_delay(10); } if (!timeout) { printf_debug("timeout\n"); @@ -570,7 +570,7 @@ /*wait for cycle complete */ timeout = 100 * 1000 * 60; // 60s is a looong timeout. while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) { - myusec_delay(10); + programmer_delay(10); } if (!timeout) { printf_debug("timeout\n"); Modified: trunk/internal.c =================================================================== --- trunk/internal.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/internal.c 2009-06-05 17:48:08 UTC (rev 578) @@ -195,6 +195,18 @@ return *(volatile uint32_t *) addr; } +void internal_delay(int usecs) +{ + /* If the delay is >1 s, use usleep because timing does not need to + * be so precise. + */ + if (usecs > 1000000) { + usleep(usecs); + } else { + myusec_delay(usecs); + } +} + /* Fallback map() for programmers which don't need special handling */ void *fallback_map(const char *descr, unsigned long phys_addr, size_t len) { Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/it87spi.c 2009-06-05 17:48:08 UTC (rev 578) @@ -220,7 +220,7 @@ * This usually takes 1-10 ms, so wait in 1 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(1000); + programmer_delay(1000); return 0; } @@ -245,7 +245,7 @@ return result; spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(10); + programmer_delay(10); } /* resume normal ops... */ OUTB(0x20, it8716f_flashport); Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/jedec.c 2009-06-05 17:48:08 UTC (rev 578) @@ -73,7 +73,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0x20, bios + 0x5555); - usleep(200); + programmer_delay(200); } void protect_jedec(chipaddr bios) @@ -82,7 +82,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xA0, bios + 0x5555); - usleep(200); + programmer_delay(200); } int probe_jedec(struct flashchip *flash) @@ -110,14 +110,14 @@ /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios + 0x5555); /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet. */ - myusec_delay(probe_timing_enter); + programmer_delay(probe_timing_enter); /* Read product ID */ id1 = chip_readb(bios); @@ -139,11 +139,11 @@ /* Issue JEDEC Product ID Exit command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(probe_timing_exit); + programmer_delay(probe_timing_exit); printf_debug("%s: id1 0x%02x, id2 0x%02x", __FUNCTION__, largeid1, largeid2); if (!oddparity(id1)) @@ -179,18 +179,18 @@ { /* Issue the Sector Erase command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x30, bios + page); - myusec_delay(10); + programmer_delay(10); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -202,18 +202,18 @@ { /* Issue the Sector Erase command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x50, bios + block); - myusec_delay(10); + programmer_delay(10); /* wait for Toggle bit ready */ toggle_ready_jedec(bios); @@ -227,18 +227,18 @@ /* Issue the JEDEC Chip Erase command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x10, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); Modified: trunk/m29f002.c =================================================================== --- trunk/m29f002.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/m29f002.c 2009-06-05 17:48:08 UTC (rev 578) @@ -29,7 +29,7 @@ chip_writeb(0xaa, bios + 0x555); chip_writeb(0x55, bios + 0xaaa); chip_writeb(0x10, bios + 0x555); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; } @@ -44,7 +44,7 @@ chip_writeb(0xaa, bios + 0x555); chip_writeb(0x55, bios + 0xaaa); chip_writeb(0x30, dst); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); /* program */ Modified: trunk/m29f400bt.c =================================================================== --- trunk/m29f400bt.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/m29f400bt.c 2009-06-05 17:48:08 UTC (rev 578) @@ -26,7 +26,7 @@ chip_writeb(0x55, bios + 0x555); chip_writeb(0xA0, bios + 0xAAA); - usleep(200); + programmer_delay(200); } void write_page_m29f400bt(chipaddr bios, uint8_t *src, @@ -42,7 +42,7 @@ /* transfer data from source to destination */ chip_writeb(*src, dst); //chip_writeb(0xF0, bios); - //usleep(5); + //programmer_delay(5); toggle_ready_jedec(dst); printf ("Value in the flash at address 0x%lx = %#x, want %#x\n", @@ -61,7 +61,7 @@ chip_writeb(0x55, bios + 0x555); chip_writeb(0x90, bios + 0xAAA); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); /* The data sheet says id2 is at (bios + 0x01) and id2 listed in @@ -73,7 +73,7 @@ chip_writeb(0x55, bios + 0x555); chip_writeb(0xF0, bios + 0xAAA); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -95,7 +95,7 @@ chip_writeb(0x55, bios + 0x555); chip_writeb(0x10, bios + 0xAAA); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; @@ -113,7 +113,7 @@ //chip_writeb(0x10, bios + 0xAAA); chip_writeb(0x30, dst); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; Modified: trunk/mx29f002.c =================================================================== --- trunk/mx29f002.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/mx29f002.c 2009-06-05 17:48:08 UTC (rev 578) @@ -34,7 +34,7 @@ chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id) @@ -55,7 +55,7 @@ chip_writeb(0x55, bios + 0x2AA); chip_writeb(0x10, bios + 0x555); - myusec_delay(100); + programmer_delay(100); toggle_ready_jedec(bios); // while ((*bios & 0x40) != 0x40) @@ -82,7 +82,7 @@ chipaddr dst = bios; chip_writeb(0xF0, bios); - myusec_delay(10); + programmer_delay(10); erase_29f002(flash); //*bios = 0xF0; #if 1 Modified: trunk/sharplhf00l04.c =================================================================== --- trunk/sharplhf00l04.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/sharplhf00l04.c 2009-06-05 17:48:08 UTC (rev 578) @@ -46,9 +46,9 @@ #endif chip_writeb(0xff, bios); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -58,7 +58,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); @@ -85,7 +85,7 @@ // put another command to get out of status register mode chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 0x01); @@ -118,7 +118,7 @@ // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); - myusec_delay(10); + programmer_delay(10); // now let's see what the register is status = wait_lhf00l04(flash->virtual_memory); print_lhf00l04_status(status); Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/spi.c 2009-06-05 17:48:08 UTC (rev 578) @@ -425,7 +425,7 @@ */ /* FIXME: We assume spi_read_status_register will never fail. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - sleep(1); + programmer_delay(1000 * 1000); return 0; } @@ -453,7 +453,7 @@ */ /* FIXME: We assume spi_read_status_register will never fail. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - sleep(1); + programmer_delay(1000 * 1000); return 0; } @@ -485,7 +485,7 @@ * This usually takes 100-4000 ms, so wait in 100 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(100 * 1000); + programmer_delay(100 * 1000); return 0; } @@ -511,7 +511,7 @@ * This usually takes 100-4000 ms, so wait in 100 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(100 * 1000); + programmer_delay(100 * 1000); return 0; } @@ -557,7 +557,7 @@ * This usually takes 15-800 ms, so wait in 10 ms steps. */ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - usleep(10 * 1000); + programmer_delay(10 * 1000); return 0; } @@ -690,7 +690,7 @@ spi_write_enable(); spi_byte_program(i, buf[i]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(10); + programmer_delay(10); } return 0; @@ -748,13 +748,13 @@ return result; spi_command(6, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(5); /* SST25VF040B Tbp is max 10us */ + programmer_delay(5); /* SST25VF040B Tbp is max 10us */ while (pos < size) { w[1] = buf[pos++]; w[2] = buf[pos++]; spi_command(3, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(5); /* SST25VF040B Tbp is max 10us */ + programmer_delay(5); /* SST25VF040B Tbp is max 10us */ } spi_write_disable(); return 0; Modified: trunk/sst28sf040.c =================================================================== --- trunk/sst28sf040.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/sst28sf040.c 2009-06-05 17:48:08 UTC (rev 578) @@ -94,16 +94,16 @@ uint8_t id1, id2; chip_writeb(RESET, bios); - myusec_delay(10); + programmer_delay(10); chip_writeb(READ_ID, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); - myusec_delay(10); + programmer_delay(10); id2 = chip_readb(bios + 0x01); chip_writeb(RESET, bios); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); if (id1 == flash->manufacture_id && id2 == flash->model_id) @@ -121,7 +121,7 @@ chip_writeb(CHIP_ERASE, bios); protect_28sf040(bios); - myusec_delay(10); + programmer_delay(10); toggle_ready_jedec(bios); return 0; Modified: trunk/stm50flw0x0x.c =================================================================== --- trunk/stm50flw0x0x.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/stm50flw0x0x.c 2009-06-05 17:48:08 UTC (rev 578) @@ -35,7 +35,7 @@ chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xA0, bios + 0x5555); - usleep(200); + programmer_delay(200); } int probe_stm50flw0x0x(struct flashchip *flash) @@ -46,11 +46,11 @@ /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios + 0x5555); - myusec_delay(40); + programmer_delay(40); /* Read product ID */ id1 = chip_readb(bios); @@ -72,11 +72,11 @@ /* Issue JEDEC Product ID Exit command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(40); + programmer_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, largeid1, largeid2); @@ -101,7 +101,7 @@ // put another command to get out of status register mode chip_writeb(0x90, bios); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); @@ -170,7 +170,7 @@ // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); - myusec_delay(10); + programmer_delay(10); wait_stm50flw0x0x(flash->virtual_memory); Modified: trunk/udelay.c =================================================================== --- trunk/udelay.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/udelay.c 2009-06-05 17:48:08 UTC (rev 578) @@ -24,10 +24,10 @@ // count to a billion. Time it. If it's < 1 sec, count to 10B, etc. unsigned long micro = 1; -void myusec_delay(int time) +void myusec_delay(int usecs) { volatile unsigned long i; - for (i = 0; i < time * micro; i++) ; + for (i = 0; i < usecs * micro; i++) ; } void myusec_calibrate_delay(void) Modified: trunk/w29ee011.c =================================================================== --- trunk/w29ee011.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/w29ee011.c 2009-06-05 17:48:08 UTC (rev 578) @@ -38,17 +38,17 @@ /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x80, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x60, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); /* Read product ID */ id1 = chip_readb(bios); @@ -56,11 +56,11 @@ /* Issue JEDEC Product ID Exit command */ chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __FUNCTION__, id1, id2); Modified: trunk/w39v040c.c =================================================================== --- trunk/w39v040c.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/w39v040c.c 2009-06-05 17:48:08 UTC (rev 578) @@ -26,22 +26,22 @@ uint8_t id1, id2, lock; chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x90, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); id1 = chip_readb(bios); id2 = chip_readb(bios + 1); lock = chip_readb(bios + 0xfff2); chip_writeb(0xAA, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); chip_writeb(0x55, bios + 0x2AAA); - myusec_delay(10); + programmer_delay(10); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(40); + programmer_delay(40); printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2); if (!oddparity(id1)) Modified: trunk/w39v080fa.c =================================================================== --- trunk/w39v080fa.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/w39v080fa.c 2009-06-05 17:48:08 UTC (rev 578) @@ -29,7 +29,7 @@ chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0x90, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); /* Read product ID */ id1 = chip_readb(bios); @@ -39,7 +39,7 @@ chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); @@ -108,7 +108,7 @@ chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0x90, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); /* Read Hardware Lock Bits */ locking = chip_readb(bios + 0xffff2); @@ -117,7 +117,7 @@ chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xF0, bios + 0x5555); - myusec_delay(10); + programmer_delay(10); printf_debug("Lockout bits:\n"); Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2009-06-05 17:04:37 UTC (rev 577) +++ trunk/wbsio_spi.c 2009-06-05 17:48:08 UTC (rev 578) @@ -159,7 +159,7 @@ OUTB(writearr[0], wbsio_spibase); OUTB(mode, wbsio_spibase + 1); - myusec_delay(10); + programmer_delay(10); if (!readcnt) return 0; @@ -203,7 +203,7 @@ for (pos = 0; pos < size; pos++) { spi_byte_program(pos, buf[pos]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(10); + programmer_delay(10); } spi_write_disable(); return 0; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
