Hello, after a few tries of me to fix the interrupt problems which occurred on the M57SLI here is the final patch from me.
The Patch fixes the following issues on M57SLI: * Interrupt routing in the MPTable which affects the following hardware parts: * PCI-E 16x Slots (blue and black) - both are working now like a charm * PCI-E 1x Slots - all three should be fine, but I have no card to test. (untested) * PCI Slots - both work fine now. This is the first and (hopefully) the last patch on this issue which gets a Signed-off-by: Harald Gutmann <[email protected]> from me. I'm really looking forward to commit this patch (which is my first one) and mark the interrupt issues on the wiki page to the M57SLI as solved. :) Kind regards, Harald Gutmann
Index: mptable.c
===================================================================
--- mptable.c (revision 4352)
+++ mptable.c (working copy)
@@ -43,7 +43,7 @@
struct mp_config_table *mc;
unsigned sbdn;
- int i,j;
+ int i,j,k;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
@@ -87,19 +87,17 @@
if (res) {
smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
}
-
- dword = 0x43c6c643;
+ dword = 0xc643c643;
pci_write_config32(dev, 0x7c, dword);
- dword = 0x81001a00;
+ dword = 0x8da01009;
pci_write_config32(dev, 0x80, dword);
- dword = 0xd0001202;
+ dword = 0x200018d2;
pci_write_config32(dev, 0x84, dword);
-
}
}
-
+
/*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
@@ -128,31 +126,37 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))
- PCI_INT(0,sbdn+1,1, 10); /* SMBus */
- PCI_INT(0,sbdn+2,0, 22); /* USB */
- PCI_INT(0,sbdn+2,1, 23); /* USB */
- PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
- PCI_INT(0,sbdn+5,0, 20); /* SATA */
- PCI_INT(0,sbdn+5,1, 23); /* SATA */
- PCI_INT(0,sbdn+5,2, 21); /* SATA */
+ PCI_INT(0,sbdn+1,1, 10); /* SMBus */
+ PCI_INT(0,sbdn+2,0, 22); /* USB */
+ PCI_INT(0,sbdn+2,1, 23); /* USB */
+ PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
+ PCI_INT(0,sbdn+4,0, 21); /* IDE */
+ PCI_INT(0,sbdn+5,0, 20); /* SATA */
+ PCI_INT(0,sbdn+5,1, 21); /* SATA */
+ PCI_INT(0,sbdn+5,2, 22); /* SATA */
+ PCI_INT(0,sbdn+8,0, 20); /* GBit Ether */
+ PCI_INT(1,0x0a,0, 18); /* Firewire */
- PCI_INT(0,sbdn+8,0, 22); /* GBit Ether */
-
/* The PCIe slots, each on its own bus */
- for(j=7; j>=2; j--) {
- if(!bus_mcp55[j]) continue;
- for(i=0;i<4;i++) { /* map all functions */
- PCI_INT(j,0,i, 16+(1+j+i)%4);
- }
- }
+ k = 1;
+ for(i=0; i<=3; i++){
+ for(j=7; j>=2; j--){
+ if(k>3) k=0;
+ PCI_INT(j,0,i, 16+k);
+ k++;
+ }
+ k--;
+ }
/* On bus 1: the physical PCI bus slots... */
- for(j=0; j<2; j++) /* on a Rev 1.x board, they are devs 7 and 8 */
- for(i=0;i<4;i++) { /* map all functions */
- PCI_INT(1,7+j,i, 16+(3+i+j)%4);
- }
- /* ... and OB FireWire */
- PCI_INT(1,0x0a,0, 18);
+ k=2;
+ for(i=0; i<=3; i++){
+ for(j=6; j<=10; j++){
+ if(k>3) k=0;
+ PCI_INT(1,j,i, 16+k);
+ k++;
+ }
+ }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
Index: cache_as_ram_auto.c
===================================================================
--- cache_as_ram_auto.c (revision 4352)
+++ cache_as_ram_auto.c (working copy)
@@ -134,10 +134,10 @@
#define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0xA8,/* GPIO40 PCI_GNT2 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0xA8,/* GPIO41 PCI_REQ2 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x48,/* GPIP60 FANCTL0 */ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x48,/* GPIO61 FANCTL1 */
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
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