On Thu, Jun 11, 2009 at 23:30, Carl-Daniel Hailfinger<[email protected]> wrote: > Ah, the common trap of MByte vs. Mbit. The chips are 4 Mbit (512 kByte), > so there won't be any overlap.
No, I'm well aware of the distinction (embedded hardware designer) you are right though, I misread the datasheet (Saw M assumed Mb because it was a ROM, looking at it again they say M byte (presumably because a lot of people don't realise the difference between Mb and MB), teach me for posting to mailing lists at 22:00 ;oD ) > Besides that, the Winbond datasheets explicitly mention that ID3 is not > used by the chips unless I'm totally misreading them. >From my datasheet (Revision A2, dated 19/12/2002); ...For accessing the 4M byte BIOS storage space, the ID[2:0] pins are inverted in the ROM and are compared to address lines [21:19]. ID[3] can be used as like active low chip-select pin. Ergo, tie ID3 high, chip effectively disabled, same outcome as using the ID2 pin as you say though. -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
