On 11.06.2009 16:15, Morgan Reed wrote: > On Thu, Jun 11, 2009 at 23:30, Carl-Daniel > Hailfinger<[email protected]> wrote: > >> Ah, the common trap of MByte vs. Mbit. The chips are 4 Mbit (512 kByte), >> so there won't be any overlap. >> > > No, I'm well aware of the distinction (embedded hardware designer)
Neat. I didn't want to imply you didn't know about the distinction, but I sometime confuse units when I'm very tired. Seems I'm not the only one. ;-) > >From my datasheet (Revision A2, dated 19/12/2002); > ...For accessing the 4M byte BIOS storage space, the ID[2:0] pins are > Whoa. 4 M byte. Evil datasheet. > Ergo, tie ID3 high, chip effectively disabled, same outcome as using > the ID2 pin as you say though. > True. My idea in using ID2 was to make the old chip available a bit lower in the address space so flashrom could access it while the other chip is stacked on top. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
