On Wed, Jun 24, 2009 at 6:36 AM, Arnaud Maye<[email protected]> wrote: > I've tried a reverse engineer approach. Plug a DIMM into the system and > launch Linux with the > legacy BIOS. lspci -xxx then shows me the IMCH BAR and implicitly the > settings doctored by the > legacy BIOS. The first try I've done was to try the r-e DRT0/DRT1 in the > coreboot RAM init code. > Not much differences so far. But anyway I've seen quite a lot of difference > around the ODT register > and such. So there is still some hope.
Have you tried 2T timing? This causes the memory controller to wait an extra cycle before sending a command. The delay can compensate for slight misconfiguration of other signal timing settings so it's a good place to start. Also try different RCOMP values. I have no idea what RCOMP is but I remember having to tweak it to get the memory to behave. --Ed -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
