On Thu, Oct 8, 2009 at 9:44 PM, ron minnich <[email protected]> wrote:
> to generate romcc code that > will work on the least-capable CPU for that socket. ... > the socket has to determine > whether MMX and SSE are set. Maybe since these options are romcc-specific they should be ROMCC_MMX & ROMCC_SSE. I just noticed that on my K8 boards SSE=0, which is confusing. Thanks, Myles -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
