On Tue, Oct 20, 2009 at 2:53 PM, Hugh Greenberg <[email protected]> wrote:
> Yes. Here is the output:
>
>
> RAM end at 0x00100000 kB
> Lower RAM end at 0x00100000 kB
> Ram3
>
OK. So it's actually hanging in RAM init, not starting the other
processors.
Here's another patch :)
Thanks,
Myles
Index: svn/src/lib/generic_sdram.c
===================================================================
--- svn.orig/src/lib/generic_sdram.c
+++ svn/src/lib/generic_sdram.c
@@ -58,6 +58,7 @@ void sdram_initialize(int controllers, c
print_debug("Ram3\r\n");
#if RAMINIT_SYSINFO == 1
+ #error "RAMINIT_SYSINFO set "
sdram_enable(controllers, ctrl, sysinfo);
#else
sdram_enable(controllers, ctrl);
Index: svn/src/mainboard/arima/hdama/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/arima/hdama/cache_as_ram_auto.c
+++ svn/src/mainboard/arima/hdama/cache_as_ram_auto.c
@@ -157,33 +157,22 @@ void cache_as_ram_main(unsigned long bis
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- static const struct mem_controller cpu[] = {
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
- .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
- },
+ static const uint16_t spd_addr [] = {
+ (0xa<<3)|0, (0xa<<3)|2, 0, 0,
+ (0xa<<3)|1, (0xa<<3)|3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
- .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
- },
+ (0xa<<3)|4, (0xa<<3)|6, 0, 0,
+ (0xa<<3)|5, (0xa<<3)|7, 0, 0,
#endif
};
int needs_reset;
+ unsigned bsp_apicid = 0;
+ struct mem_controller ctrl[8];
+ unsigned nodes;
if (bist == 0) {
- init_cpus(cpu_init_detectedx);
+ bsp_apicid = init_cpus(cpu_init_detectedx);
}
pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -200,6 +189,7 @@ void real_main(unsigned long bist, unsig
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
+ wait_all_other_cores_started(bsp_apicid);
#endif
// automatically set that for you, but you might meet tight space
needs_reset |= ht_setup_chains_x();
@@ -209,11 +199,17 @@ void real_main(unsigned long bist, unsig
soft_reset();
}
+ allow_all_aps_stop(bsp_apicid);
+
+ nodes = get_nodes();
+
+ fill_mem_ctrl(nodes, ctrl, spd_addr);
+
enable_smbus();
memreset_setup();
- sdram_initialize(ARRAY_SIZE(cpu), cpu);
- post_cache_as_ram();
+ sdram_initialize(nodes, ctrl);
+ post_cache_as_ram();
}
Index: svn/src/northbridge/amd/amdk8/raminit.c
===================================================================
--- svn.orig/src/northbridge/amd/amdk8/raminit.c
+++ svn/src/northbridge/amd/amdk8/raminit.c
@@ -2237,6 +2237,7 @@ static void sdram_enable(int controllers
die("No memory\n");
}
+ printk_debug("Before starting clocks: ");
/* Before enabling memory start the memory clocks */
for (i = 0; i < controllers; i++) {
uint32_t dch;
@@ -2256,10 +2257,12 @@ static void sdram_enable(int controllers
}
}
+ printk_debug("Before memreset: ");
/* We need to wait a minimum of 20 MEMCLKS to enable the InitDram */
/* And if necessary toggle the the reset on the dimms by hand */
memreset(controllers, ctrl);
+ printk_debug("Before controllers loop: ");
for (i = 0; i < controllers; i++) {
uint32_t dcl, dch;
if (!controller_present(ctrl + i))
@@ -2292,6 +2295,7 @@ static void sdram_enable(int controllers
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
}
+ printk_debug("Before 2nd controllers loop: ");
for (i = 0; i < controllers; i++) {
uint32_t dcl, dch;
if (!controller_present(ctrl + i))
@@ -2328,6 +2332,7 @@ static void sdram_enable(int controllers
printk_debug(" done\n");
}
+ printk_debug("Before hole: ");
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
// init hw mem hole here
/* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
--
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