On Wed, Oct 21, 2009 at 3:03 PM, Hugh Greenberg <[email protected]> wrote:
> Alight! It booted and loaded seabios. Attached is the entire output.
Great. So the two problems were init_timer and pci_check_direct, right?
I've attached the two patches.
Signed-off-by: Myles Watson <[email protected]>
> One thing though, it failed to load gpxe. The only thing related to this
> that looks like an error is:
>
> File pci14e4,16a6.rom is of type 63000000 instead oftype 30
> and this
> PCI Expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
> Incorrect Expansion ROM Header Signature 0000
>
This should be OK because you don't want it to run before Coreboot is
through. I think SeaBIOS should run it, right?
I don't know anything about gpxe. I'm assuming you followed the
instructions here:
http://www.coreboot.org/SeaBIOS#Adding_gpxe_support
Did you try pushing f12 to see the boot menu?
Thanks,
Myles
Index: svn/src/arch/i386/lib/pci_ops_auto.c
===================================================================
--- svn.orig/src/arch/i386/lib/pci_ops_auto.c
+++ svn/src/arch/i386/lib/pci_ops_auto.c
@@ -47,6 +47,9 @@ const struct pci_bus_operations *pci_che
{
unsigned int tmp;
+ printk_debug("%s\n", __func__);
+ printk_debug("PCI: Forcing configuration type 1\n");
+ return &pci_cf8_conf1;
/*
* Check if configuration type 1 works.
*/
Index: svn/src/mainboard/arima/hdama/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/arima/hdama/cache_as_ram_auto.c
+++ svn/src/mainboard/arima/hdama/cache_as_ram_auto.c
@@ -157,33 +157,22 @@ void cache_as_ram_main(unsigned long bis
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- static const struct mem_controller cpu[] = {
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
- .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
- },
+ static const uint16_t spd_addr [] = {
+ (0xa<<3)|0, (0xa<<3)|2, 0, 0,
+ (0xa<<3)|1, (0xa<<3)|3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
- .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
- },
+ (0xa<<3)|4, (0xa<<3)|6, 0, 0,
+ (0xa<<3)|5, (0xa<<3)|7, 0, 0,
#endif
};
int needs_reset;
+ unsigned bsp_apicid = 0;
+ struct mem_controller ctrl[8];
+ unsigned nodes;
if (bist == 0) {
- init_cpus(cpu_init_detectedx);
+ bsp_apicid = init_cpus(cpu_init_detectedx);
}
pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -200,7 +189,10 @@ void real_main(unsigned long bist, unsig
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
+ wait_all_other_cores_started(bsp_apicid);
#endif
+ init_timer(); /* This is needed to be able to call udelay() */
+
// automatically set that for you, but you might meet tight space
needs_reset |= ht_setup_chains_x();
@@ -209,11 +201,17 @@ void real_main(unsigned long bist, unsig
soft_reset();
}
+ allow_all_aps_stop(bsp_apicid);
+
+ nodes = get_nodes();
+
+ fill_mem_ctrl(nodes, ctrl, spd_addr);
+
enable_smbus();
memreset_setup();
- sdram_initialize(ARRAY_SIZE(cpu), cpu);
- post_cache_as_ram();
+ sdram_initialize(nodes, ctrl);
+ post_cache_as_ram();
}
--
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