Myles,
Setting it to 1 or 2 gives what looks like the same output. It causes
coreboot to fail with the following error:
Initializing CBMEM area to 0x3fff0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 3fff0200...ok
High Tables Base is 3fff0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x3fff0400... done.
PIRQ table: 176 bytes.
Looking for bad PCIX MHz input
get_pbus: dev is NULL!
--
Hugh Greenberg
Myles Watson wrote:
It turns out that SB_HT_CHAIN_ON_BUS_0 was set incorrectly. I should
have had you test if it should have been 2, but at least setting it to
1 should let SeaBIOS find your devices.
Thanks,
Myles
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