Hello I have biostar M6TLD, it survives already raminit, patch is in attachment, also log from boot and config. Payload is uncompressed since i had problems with error in decompression from lzma, and current payload is coreinfo.
Machine reboots at point indicated in log but only difference between next loops is like that one below, diff between two restarts from same log. Jumping to image. coreboot-2.3 Thu Dec 3 00:30:36 CET 2009 booting... Calibrating delay loop... -end 1ee10434f, start 1c570413d +end 2c5cfc8a0, start 29d2fc6b1 32-bit delta 650 calibrate_tsc 32-bit result is 650 clocks_per_usec: 650 Anyone has idea how to debug why it restarts? I am not placing signed off yet as it don't work unless producing endless stream of coreboot attempts to start is working. best regards Maciej -- Maciej Pijanka reg. Linux user #133161
# # Automatically generated make config: don't edit # coreboot version: 2.3 # Thu Dec 3 00:56:17 2009 # # # General setup # CONFIG_EXPERT=y CONFIG_LOCALVERSION="" # # Mainboard # # CONFIG_VENDOR_ABIT is not set # CONFIG_VENDOR_ADVANTECH is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_ARIMA is not set # CONFIG_VENDOR_ARTEC_GROUP is not set # CONFIG_VENDOR_ASI is not set # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AXUS is not set # CONFIG_VENDOR_AZZA is not set # CONFIG_VENDOR_BCOM is not set CONFIG_VENDOR_BIOSTAR=y # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set # CONFIG_VENDOR_DELL is not set # CONFIG_VENDOR_DIGITAL_LOGIC is not set # CONFIG_VENDOR_EAGLELION is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_IEI is not set # CONFIG_VENDOR_INTEL is not set # CONFIG_VENDOR_IWILL is not set # CONFIG_VENDOR_JETWAY is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set # CONFIG_VENDOR_NEWISYS is not set # CONFIG_VENDOR_NVIDIA is not set # CONFIG_VENDOR_OLPC is not set # CONFIG_VENDOR_PC_ENGINES is not set # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set # CONFIG_VENDOR_SUPERMICRO is not set # CONFIG_VENDOR_TECHNEXION is not set # CONFIG_VENDOR_TECHNOLOGIC is not set # CONFIG_VENDOR_TELEVIDEO is not set # CONFIG_VENDOR_THOMSON is not set # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set CONFIG_MAINBOARD_VENDOR="Biostar" CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x0 CONFIG_MAINBOARD_DIR="biostar/m6tld" CONFIG_MAINBOARD_PART_NUMBER="M6TLD" # CONFIG_HAVE_OPTION_TABLE is not set CONFIG_IRQ_SLOT_COUNT=5 CONFIG_RAMBASE=0x100000 CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0 CONFIG_LB_CKS_RANGE_END=125 CONFIG_LB_CKS_LOC=126 CONFIG_MAX_CPUS=1 CONFIG_MAX_PHYSICAL_CPUS=1 # CONFIG_USE_INIT is not set CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0 CONFIG_SERIAL_CPU_INIT=y CONFIG_RAMTOP=0x200000 CONFIG_HEAP_SIZE=0x4000 CONFIG_ACPI_SSDTX_NUM=0 # CONFIG_BOARD_BIOSTAR_M6TBA is not set CONFIG_BOARD_BIOSTAR_M6TLD=y CONFIG_HAVE_INIT_TIMER=y CONFIG_LB_CKS_RANGE_START=49 # CONFIG_PCI_64BIT_PREF_MEM is not set CONFIG_HAVE_FALLBACK_BOOT=y CONFIG_USE_FALLBACK_IMAGE=y # CONFIG_WAIT_BEFORE_CPUS_INIT is not set # CONFIG_K8_REV_F_SUPPORT is not set CONFIG_STACK_SIZE=0x8000 CONFIG_VGA_ROM_RUN=y CONFIG_PCI_ROM_RUN=y CONFIG_COREBOOT_ROMSIZE_KB_128=y # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set # CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set CONFIG_COREBOOT_ROMSIZE_KB=128 CONFIG_ROM_SIZE=0x20000 CONFIG_ARCH_X86=y # CONFIG_AP_IN_SIPI_WAIT is not set CONFIG_ARCH="i386" CONFIG_ROMBASE=0xffff0000 CONFIG_ROM_IMAGE_SIZE=0x10000 CONFIG_MAX_REBOOT_CNT=3 # # Chipset # # # CPU # CONFIG_XIP_ROM_BASE=0xfffe0000 CONFIG_XIP_ROM_SIZE=0x20000 CONFIG_CPU_ADDR_BITS=36 CONFIG_CPU_INTEL_SLOT_2=y CONFIG_UDELAY_IO=y # CONFIG_UDELAY_LAPIC is not set # CONFIG_UDELAY_TSC is not set # CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 is not set # CONFIG_USE_DCACHE_RAM is not set # CONFIG_SMP is not set CONFIG_VAR_MTRR_HOLE=y # # Northbridge # CONFIG_NORTHBRIDGE_INTEL_I440LX=y CONFIG_VIDEO_MB=0 # # Southbridge # CONFIG_SOUTHBRIDGE_INTEL_I82371EB=y CONFIG_ID_SECTION_OFFSET=0x10 # # Super I/O # CONFIG_SUPERIO_SMSC_SMSCSUPERIO=y # # Devices # CONFIG_VGA_BRIDGE_SETUP=y CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y # CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set # CONFIG_PCI_OPTION_ROM_RUN_X86EMU is not set # CONFIG_CONSOLE_VGA_MULTI is not set # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_AGP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y CONFIG_PCI_BUS_SEGN_BITS=0 CONFIG_LOGICAL_CPUS=y CONFIG_COREBOOT_V2=y CONFIG_COREBOOT_V4=y # CONFIG_DEBUG is not set # CONFIG_USE_PRINTK_IN_CAR is not set # CONFIG_USE_OPTION_TABLE is not set # CONFIG_MMCONF_SUPPORT_DEFAULT is not set # CONFIG_MMCONF_SUPPORT is not set # # Console options # CONFIG_CONSOLE_SERIAL8250=y CONFIG_CONSOLE_SERIAL_COM1=y # CONFIG_CONSOLE_SERIAL_COM2 is not set # CONFIG_CONSOLE_SERIAL_COM3 is not set # CONFIG_CONSOLE_SERIAL_COM4 is not set CONFIG_TTYS0_BASE=0x3f8 CONFIG_CONSOLE_SERIAL_115200=y # CONFIG_CONSOLE_SERIAL_57600 is not set # CONFIG_CONSOLE_SERIAL_38400 is not set # CONFIG_CONSOLE_SERIAL_19200 is not set # CONFIG_CONSOLE_SERIAL_9600 is not set CONFIG_TTYS0_BAUD=115200 CONFIG_TTYS0_LCS=3 # CONFIG_SERIAL_POST is not set # CONFIG_USBDEBUG_DIRECT is not set # CONFIG_CONSOLE_VGA is not set # CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST is not set CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 # CONFIG_CONSOLE_BTEXT is not set # CONFIG_CONSOLE_SROM is not set # CONFIG_CONSOLE_LOGBUF is not set # CONFIG_HAVE_ACPI_RESUME is not set # CONFIG_HAVE_FAILOVER_BOOT is not set # CONFIG_USE_FAILOVER_IMAGE is not set # CONFIG_HAVE_HARD_RESET is not set # CONFIG_HAVE_MAINBOARD_RESOURCES is not set # CONFIG_HAVE_MOVNTI is not set # CONFIG_PIRQ_ROUTE is not set # CONFIG_HAVE_SMI_HANDLER is not set # CONFIG_PCI_IO_CFG_EXT is not set # CONFIG_IOAPIC is not set # CONFIG_USE_WATCHDOG_ON_BOOT is not set # CONFIG_VGA is not set # CONFIG_GFXUMA is not set CONFIG_HAVE_LOW_TABLES=y CONFIG_HAVE_HIGH_TABLES=y CONFIG_HAVE_PIRQ_TABLE=y # CONFIG_GENERATE_ACPI_TABLES is not set # CONFIG_GENERATE_MP_TABLE is not set CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_WRITE_HIGH_TABLES=y # # System tables # # CONFIG_MULTIBOOT is not set # # Payload # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y CONFIG_FALLBACK_PAYLOAD_FILE="payload.elf" # CONFIG_COMPRESSED_PAYLOAD_LZMA is not set # CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set # # VGA BIOS # # CONFIG_VGA_BIOS is not set # # Debugging # CONFIG_GDB_STUB=y # CONFIG_LIFT_BSP_APIC_ID is not set # CONFIG_AP_CODE_IN_CAR is not set # CONFIG_ENABLE_APIC_EXT_ID is not set # CONFIG_WARNINGS_ARE_ERRORS is not set
minicom.cap
Description: application/cap
Index: src/mainboard/biostar/Kconfig =================================================================== --- src/mainboard/biostar/Kconfig (revision 4974) +++ src/mainboard/biostar/Kconfig (working copy) @@ -23,6 +23,7 @@ depends on VENDOR_BIOSTAR source "src/mainboard/biostar/m6tba/Kconfig" +source "src/mainboard/biostar/m6tld/Kconfig" endchoice Index: src/mainboard/biostar/m6tld/Kconfig =================================================================== --- src/mainboard/biostar/m6tld/Kconfig (revision 0) +++ src/mainboard/biostar/m6tld/Kconfig (revision 0) @@ -0,0 +1,55 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <[email protected]> +## Copyright (C) 2009 Maciej Pijanka <[email protected]> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_BIOSTAR_M6TLD + bool "M6TLD" + select ARCH_X86 + select CPU_INTEL_SLOT_2 + select NORTHBRIDGE_INTEL_I440LX + select SOUTHBRIDGE_INTEL_I82371EB + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select UDELAY_IO +# select PCI_ROM_RUN +# select CONSOLE_VGA + help + Biostar M6TLD mainboard. + +config MAINBOARD_DIR + string + default biostar/m6tld + depends on BOARD_BIOSTAR_M6TLD + +config MAINBOARD_PART_NUMBER + string + default "M6TLD" + depends on BOARD_BIOSTAR_M6TLD + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_BIOSTAR_M6TLD + +config IRQ_SLOT_COUNT + int + default 5 + depends on BOARD_BIOSTAR_M6TLD + Index: src/mainboard/biostar/m6tld/Config.lb =================================================================== --- src/mainboard/biostar/m6tld/Config.lb (revision 0) +++ src/mainboard/biostar/m6tld/Config.lb (revision 0) @@ -0,0 +1,131 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Uwe Hermann <[email protected]> +## Copyright (C) 2009 Maciej Pijanka <[email protected]> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 +#default CONFIG_USE_FALLBACK_IMAGE = 0 +#default CONFIG_HAVE_FALLBACK_BOOT = 0 +#default CONFIG_ROM_IMAGE_SIZE = 0xB000 +#default CONFIG_FALLBACK_SIZE = 0x0000 +include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 + +arch i386 end +driver mainboard.o +if CONFIG_GENERATE_PIRQ_TABLE + object irq_tables.o +end +makerule ./failover.E + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if CONFIG_USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if CONFIG_USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu_enable.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx_disable.inc + +dir /pc80 +config chip.h + +chip northbridge/intel/i440lx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 off end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge (its ab really but..) + device pci 7.0 on # ISA bridge + chip superio/smsc/smscsuperio # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.8 on # Aux I/O + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Index: src/mainboard/biostar/m6tld/devicetree.cb =================================================================== --- src/mainboard/biostar/m6tld/devicetree.cb (revision 0) +++ src/mainboard/biostar/m6tld/devicetree.cb (revision 0) @@ -0,0 +1,53 @@ +chip northbridge/intel/i440lx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 off end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/smsc/smscsuperio # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.8 on # Aux I/O + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end +end Index: src/mainboard/biostar/m6tld/Makefile.inc =================================================================== --- src/mainboard/biostar/m6tld/Makefile.inc (revision 0) +++ src/mainboard/biostar/m6tld/Makefile.inc (revision 0) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Maciej Pijanka <[email protected]> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +include $(src)/mainboard/Makefile.romccboard.inc + +#ROMCCFLAGS := -mcpu=i386 -O - Index: src/mainboard/biostar/m6tld/irq_tables.c =================================================================== --- src/mainboard/biostar/m6tld/irq_tables.c (revision 0) +++ src/mainboard/biostar/m6tld/irq_tables.c (revision 0) @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Maciej Pijanka <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifdef GETPIR /* TODO: Drop this when copying to coreboot. */ +#include "pirq_routing.h" /* TODO: Drop this when copying to coreboot. */ +#else /* TODO: Drop this when copying to coreboot. */ +#include <arch/pirq_routing.h> +#endif /* TODO: Drop this when copying to coreboot. */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x07 << 3) | 0x0, /* Interrupt router dev */ + 0x9c00, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x7000, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x38, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x08 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0x0}, + {0x00, (0x09 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0x0}, + {0x00, (0x0a << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x3, 0x0}, + {0x00, (0x07 << 3) | 0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x07 << 3) | 0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Index: src/mainboard/biostar/m6tld/Options.lb =================================================================== --- src/mainboard/biostar/m6tld/Options.lb (revision 0) +++ src/mainboard/biostar/m6tld/Options.lb (revision 0) @@ -0,0 +1,99 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Uwe Hermann <[email protected]> +## Copyright (C) 2009 Maciej Pijanka <[email protected]> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses CONFIG_GENERATE_MP_TABLE +uses CONFIG_GENERATE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_CROSS_COMPILE +uses CC +uses HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses CONFIG_ID_SECTION_OFFSET + +default CONFIG_ROM_SIZE = 128 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_GENERATE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default CONFIG_GENERATE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 +default CONFIG_ID_SECTION_OFFSET=0x80 + +end Index: src/mainboard/biostar/m6tld/auto.c =================================================================== --- src/mainboard/biostar/m6tld/auto.c (revision 0) +++ src/mainboard/biostar/m6tld/auto.c (revision 0) @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann <[email protected]> + * Copyright (C) 2009 Maciej Pijanka <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> + +#include <arch/hlt.h> +#include <stdlib.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" + +#include "lib/ramtest.c" + +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" +#include "northbridge/intel/i440lx/raminit.h" +#include "lib/debug.c" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440lx/raminit.c" +//#include "northbridge/intel/i440bx/debug.c" + +#if 0 +static void check_up_mem(void) { + uint32_t reg32 = pci_read_config8(NB, DRB7) * 8 * 1024 * 1024; + ram_check(1024*1024, reg32); +} +#endif + +static void main(unsigned long bist) +{ + if (bist == 0) + early_mtrr_init(); + + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + enable_smbus(); + //dump_spd_registers(); + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); + //ram_check(0, 640 * 1024); + //check_up_mem(); + i82371eb_enable_rom(PCI_DEV(0, 7, 0)); +} Index: src/mainboard/biostar/m6tld/chip.h =================================================================== --- src/mainboard/biostar/m6tld/chip.h (revision 0) +++ src/mainboard/biostar/m6tld/chip.h (revision 0) @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Maciej Pijanka <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; Index: src/mainboard/biostar/m6tld/mainboard.c =================================================================== --- src/mainboard/biostar/m6tld/mainboard.c (revision 0) +++ src/mainboard/biostar/m6tld/mainboard.c (revision 0) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Maciej Pijanka <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("Biostar M6TLD Mainboard") +}; Index: targets/biostar/m6tld/Config.lb =================================================================== --- targets/biostar/m6tld/Config.lb (revision 0) +++ targets/biostar/m6tld/Config.lb (revision 0) @@ -0,0 +1,57 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Uwe Hermann <[email protected]> +## Copyright (C) 2009 Maciej Pijanka <[email protected]> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target m6tld +mainboard biostar/m6tld + +# Note: The original flash ROM chip is 128 KB. +# Board will FRY larger chip unless some soldering is involved. After some +# soldering (moving one resistor) board can do 256 KB chip. Anything larger +# requires more soldering with adding missing wires. +option CONFIG_ROM_SIZE = 256 * 1024 + +option CONFIG_MAINBOARD_VENDOR = "Biostar" +option CONFIG_MAINBOARD_PART_NUMBER = "M6TLD" + +CONFIG_ROM_IMAGE_SIZE=0x4000 +CONFIG_FALLBACK_SIZE=0x0000 + +#option CONFIG_IRQ_SLOT_COUNT = 5 + +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 + +option CONFIG_CONSOLE_VGA = 0 +option CONFIG_PCI_ROM_RUN = 0 + +romimage "normal" + option CONFIG_USE_FALLBACK_IMAGE = 0 + option COREBOOT_EXTRA_VERSION = ".0Normal" + payload /tmp/filo.elf +end + +romimage "fallback" + option CONFIG_USE_FALLBACK_IMAGE = 1 + option COREBOOT_EXTRA_VERSION = ".0Fallback" + payload /tmp/filo.elf +end + +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
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