Hi,
batch of patches:
20100103-1-use-selected-udelay-function
Kconfig used the TSC timer unconditionally.
20100103-2-include-forgotten-intel-socket
An intel socket is still commented out - probably forgotten in the mass
conversion effort
20100103-3-intel-cpus-have-movnti
Set HAVE_MOVNTI per CPU for intels as defined in Config.lb files (only
where Kconfig files for CPUs already exist)
20100103-4-tinybootblock-for-intel-cpus
Add tinybootblock handling to Intel's CAR code:
- avoid the normal/fallback decision (we don't have __normal_image, and
we'd use CBFS for loading anyway)
- use CONFIG_XIP_ROM_BASE as external symbol, filled in by the linker.
Necessary to match the XIP region with the place where the romstage ends
up in (see next patch)
20100103-5-retarget-xip-base-for-romstage
- Add proper CONFIG_XIP_ROM_BASE to location.ld (used when linking the
romstage)
20100103-6-clean-up-kontron-config
(might not apply cleanly due to manual dissection into patches -6 and -7)
- HAVE_ACPI_SLIC is not a Kconfig variable (no CONFIG_ prefix, for starters)
- HAVE_MOVNTI is defined per-CPU, not per-board (and with -3 it actually is)
20100103-7-tinybootblock-for-kontron-986lcd-m
- changes necessary to make Kontron use tinybootblock
Signed-off-by: Patrick Georgi <[email protected]>
Index: src/cpu/x86/lapic/Makefile.inc
===================================================================
--- src/cpu/x86/lapic/Makefile.inc (revision 4995)
+++ src/cpu/x86/lapic/Makefile.inc (working copy)
@@ -1,4 +1,4 @@
obj-y += lapic.o
obj-y += lapic_cpu_init.o
obj-y += secondary.o
-
+obj-$(CONFIG_UDELAY_LAPIC) += apic_timer.o
Index: src/cpu/x86/tsc/Makefile.inc
===================================================================
--- src/cpu/x86/tsc/Makefile.inc (revision 4995)
+++ src/cpu/x86/tsc/Makefile.inc (working copy)
@@ -1,2 +1,2 @@
-obj-y += delay_tsc.o
+obj-$(CONFIG_UDELAY_TSC) += delay_tsc.o
Index: src/cpu/intel/Kconfig
===================================================================
--- src/cpu/intel/Kconfig (revision 4995)
+++ src/cpu/intel/Kconfig (working copy)
@@ -11,7 +11,7 @@
source src/cpu/intel/socket_mFCPGA478/Kconfig
source src/cpu/intel/socket_mPGA478/Kconfig
source src/cpu/intel/socket_mPGA479M/Kconfig
-#source src/cpu/intel/socket_mPGA603/Kconfig
+source src/cpu/intel/socket_mPGA603/Kconfig
source src/cpu/intel/socket_mPGA604/Kconfig
source src/cpu/intel/socket_PGA370/Kconfig
source src/cpu/intel/socket_441/Kconfig
Index: src/cpu/intel/model_106cx/Kconfig
===================================================================
--- src/cpu/intel/model_106cx/Kconfig (revision 4995)
+++ src/cpu/intel/model_106cx/Kconfig (working copy)
@@ -1,3 +1,4 @@
config CPU_INTEL_ATOM_230
bool
select SMP
+ select HAVE_MOVNTI
Index: src/cpu/intel/model_6ex/Kconfig
===================================================================
--- src/cpu/intel/model_6ex/Kconfig (revision 4995)
+++ src/cpu/intel/model_6ex/Kconfig (working copy)
@@ -1,3 +1,4 @@
config CPU_INTEL_CORE
bool
select SMP
+ select HAVE_MOVNTI
Index: src/cpu/intel/model_106cx/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_106cx/cache_as_ram.inc (revision 4995)
+++ src/cpu/intel/model_106cx/cache_as_ram.inc (working copy)
@@ -114,7 +114,13 @@
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#undef CONFIG_XIP_ROM_BASE
+ movl $CONFIG_XIP_ROM_BASE, %eax
+ orl $MTRR_TYPE_WRBACK, %eax
+#else
movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#endif
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
Index: src/cpu/intel/model_106cx/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_106cx/cache_as_ram_disable.c (revision 4995)
+++ src/cpu/intel/model_106cx/cache_as_ram_disable.c (working copy)
@@ -25,6 +25,7 @@
{
unsigned int cpu_reset = 0;
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
@@ -46,6 +47,7 @@
);
fallback_image:
#endif
+#endif
real_main(bist);
Index: src/cpu/intel/model_6ex/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_6ex/cache_as_ram.inc (revision 4995)
+++ src/cpu/intel/model_6ex/cache_as_ram.inc (working copy)
@@ -104,7 +104,13 @@
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#undef CONFIG_XIP_ROM_BASE
+ movl $CONFIG_XIP_ROM_BASE, %eax
+ orl $MTRR_TYPE_WRBACK, %eax
+#else
movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#endif
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
Index: src/cpu/intel/model_6ex/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_6ex/cache_as_ram_disable.c (revision 4995)
+++ src/cpu/intel/model_6ex/cache_as_ram_disable.c (working copy)
@@ -27,6 +27,7 @@
{
unsigned int cpu_reset = 0;
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
@@ -48,6 +49,7 @@
);
fallback_image:
#endif
+#endif
real_main(bist);
Index: src/cpu/intel/model_6fx/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_6fx/cache_as_ram.inc (revision 4995)
+++ src/cpu/intel/model_6fx/cache_as_ram.inc (working copy)
@@ -111,7 +111,13 @@
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#undef CONFIG_XIP_ROM_BASE
+ movl $CONFIG_XIP_ROM_BASE, %eax
+ orl $MTRR_TYPE_WRBACK, %eax
+#else
movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#endif
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
Index: src/cpu/intel/model_6fx/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_6fx/cache_as_ram_disable.c (revision 4995)
+++ src/cpu/intel/model_6fx/cache_as_ram_disable.c (working copy)
@@ -27,6 +27,7 @@
{
unsigned int cpu_reset = 0;
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
@@ -48,6 +49,7 @@
);
fallback_image:
#endif
+#endif
real_main(bist);
Index: src/arch/i386/Makefile.tinybootblock.inc
===================================================================
--- src/arch/i386/Makefile.tinybootblock.inc (revision 4995)
+++ src/arch/i386/Makefile.tinybootblock.inc (working copy)
@@ -73,7 +73,7 @@
printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld
$(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin
fallback/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt
cat $(obj)/location.txt >> $(obj)/location.ld
- printf ";\n" >> $(obj)/location.ld
+ printf ';\nCONFIG_XIP_ROM_BASE = CONFIG_ROMBASE & ~(CONFIG_XIP_ROM_SIZE
- 1);\n' >> $(obj)/location.ld
$(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj)
-T $(obj)/romstage/ldscript.ld $(initobjs)
$(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map
$(OBJCOPY) -O binary $(obj)/romstage.elf $@
Index: src/mainboard/kontron/986lcd-m/Kconfig
===================================================================
--- src/mainboard/kontron/986lcd-m/Kconfig (revision 4995)
+++ src/mainboard/kontron/986lcd-m/Kconfig (working copy)
@@ -21,4 +21,3 @@
select IOAPIC
select USE_DCACHE_RAM
select GFXUMA
- select HAVE_MOVNTI
@@ -72,8 +71,3 @@
string
default "amipci_01.20"
depends on BOARD_KONTRON_986LCD_M
-
-config HAVE_ACPI_SLIC
- bool
- default n
- depends on BOARD_KONTRON_986LCD_M
Index: src/mainboard/kontron/986lcd-m/Kconfig
===================================================================
--- src/mainboard/kontron/986lcd-m/Kconfig (revision 4995)
+++ src/mainboard/kontron/986lcd-m/Kconfig (working copy)
@@ -21,6 +21,7 @@
select IOAPIC
select USE_DCACHE_RAM
select GFXUMA
+ select TINY_BOOTBLOCK
config MAINBOARD_DIR
string
Index: src/mainboard/kontron/986lcd-m/Makefile.inc
===================================================================
--- src/mainboard/kontron/986lcd-m/Makefile.inc (revision 4995)
+++ src/mainboard/kontron/986lcd-m/Makefile.inc (working copy)
@@ -40,18 +40,12 @@
initobj-y += crt0.o
# FIXME in $(top)/Makefile
-crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
-crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/arch/i386/lib/id.inc
crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc
crt0-y += auto.inc
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
-ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
-ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/arch/i386/lib/id.lds
-ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds
ifdef POST_EVALUATION
--
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