Thank you for the ACKs, commited as r4996.
Here's an updated set of patches which also fixes the udelay issues the
previous set brought up (see below)
Am 03.01.2010 23:22, schrieb Stefan Reinauer:
>> 20100103-4-tinybootblock-for-intel-cpus
>> Add tinybootblock handling to Intel's CAR code:
>> - avoid the normal/fallback decision (we don't have __normal_image, and
>> we'd use CBFS for loading anyway)
>> - use CONFIG_XIP_ROM_BASE as external symbol, filled in by the linker.
>> Necessary to match the XIP region with the place where the romstage ends
>> up in (see next patch)
>>
>>
> +#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
> +#undef CONFIG_XIP_ROM_BASE
> + movl $CONFIG_XIP_ROM_BASE, %eax
> + orl $MTRR_TYPE_WRBACK, %eax
> +#else
> movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
> +#endif
>
> This looks very odd... I'd see why you'd do the undef, given the next
> patch, but why produce the register value at runtime?
> Since this is not a CONFIG variable in tinybootblock, maybe it would
> make sense to call it differently instead of undef'ing it?
> I.e. AUTO_CALCULATED_XIP_ROM_BASE (or something better ;)
>
AUTO_XIP_ROM_BASE, and "orl $MTRR_TYPE_WRBACK, %eax" in all code paths.
For reference (we discussed this off list): orl (or some other hack) is
necessary because AUTO_XIP_ROM_BASE (as it is now called) is included by
the linker. The assembler has no idea how to cope with
"external-reference | constant", as far as I know.
>> 20100103-5-retarget-xip-base-for-romstage
>> - Add proper CONFIG_XIP_ROM_BASE to location.ld (used when linking the
>> romstage)
>>
>>
> I guess this is needed for the patch above?
>
Yes, I merged those two patches for clarity (20100104-3):
20100104-1-fix-udelay-on-kconfig
We used to use TSC for udelay on all boards. Now there wasn't a default
in case the configuration didn't say anything about timers, which
failed. The behaviour matches newconfig's now, using UDELAY_IO in case
nothing else is selected
20100104-2-use-TSC-on-via-c7
via c7 knows TSC, so use that.
20100104-3-tinybootblock-and-proper-xip-base-on-intel-cpus
Tinybootblock support for intel CPUs, and an updated mechanism to set
the XIP area to the right location (otherwise the characters on serial
can be counted by sight)
20100104-4-kontron-with-tinybootblock-and-options-cleanup
Activate tinybootblock for the kontron/986lcd-m board, and clean up the
options: MOVNTI is activated per-cpu, HAVE_ACPI_SLIC is not a kconfig
variable.
20100104-4 is the kontron stuff from yesterday's patchset, unchanged but
merged.
Signed-off-by: Patrick Georgi <[email protected]>
Index: src/Kconfig
===================================================================
--- src/Kconfig (revision 4995)
+++ src/Kconfig (working copy)
@@ -186,6 +186,7 @@
config HAVE_INIT_TIMER
bool
+ default n if UDELAY_IO
default y
config HAVE_MAINBOARD_RESOURCES
Index: src/cpu/x86/Kconfig
===================================================================
--- src/cpu/x86/Kconfig (revision 4995)
+++ src/cpu/x86/Kconfig (working copy)
@@ -8,6 +8,7 @@
config UDELAY_IO
bool
+ default y if !UDELAY_LAPIC && !UDELAY_TSC
default n
config UDELAY_LAPIC
Index: src/cpu/via/model_c7/Kconfig
===================================================================
--- src/cpu/via/model_c7/Kconfig (revision 4995)
+++ src/cpu/via/model_c7/Kconfig (working copy)
@@ -1,2 +1,3 @@
config CPU_VIA_C7
bool
+ select UDELAY_TSC
Index: src/cpu/intel/model_106cx/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_106cx/cache_as_ram_disable.c (revision 4995)
+++ src/cpu/intel/model_106cx/cache_as_ram_disable.c (working copy)
@@ -25,6 +25,7 @@
{
unsigned int cpu_reset = 0;
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
@@ -46,6 +47,7 @@
);
fallback_image:
#endif
+#endif
real_main(bist);
Index: src/cpu/intel/model_106cx/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_106cx/cache_as_ram.inc (revision 4995)
+++ src/cpu/intel/model_106cx/cache_as_ram.inc (working copy)
@@ -114,7 +114,13 @@
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
- movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+ movl $REAL_XIP_ROM_BASE, %eax
+ orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
Index: src/cpu/intel/model_6ex/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_6ex/cache_as_ram_disable.c (revision 4995)
+++ src/cpu/intel/model_6ex/cache_as_ram_disable.c (working copy)
@@ -27,6 +27,7 @@
{
unsigned int cpu_reset = 0;
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
@@ -48,6 +49,7 @@
);
fallback_image:
#endif
+#endif
real_main(bist);
Index: src/cpu/intel/model_6ex/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_6ex/cache_as_ram.inc (revision 4995)
+++ src/cpu/intel/model_6ex/cache_as_ram.inc (working copy)
@@ -104,7 +104,13 @@
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
- movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+ movl $REAL_XIP_ROM_BASE, %eax
+ orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
Index: src/cpu/intel/model_6fx/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_6fx/cache_as_ram_disable.c (revision 4995)
+++ src/cpu/intel/model_6fx/cache_as_ram_disable.c (working copy)
@@ -27,6 +27,7 @@
{
unsigned int cpu_reset = 0;
+#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
@@ -48,6 +49,7 @@
);
fallback_image:
#endif
+#endif
real_main(bist);
Index: src/cpu/intel/model_6fx/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_6fx/cache_as_ram.inc (revision 4995)
+++ src/cpu/intel/model_6fx/cache_as_ram.inc (working copy)
@@ -111,7 +111,13 @@
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
- movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+ movl $REAL_XIP_ROM_BASE, %eax
+ orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
Index: src/arch/i386/Makefile.tinybootblock.inc
===================================================================
--- src/arch/i386/Makefile.tinybootblock.inc (revision 4995)
+++ src/arch/i386/Makefile.tinybootblock.inc (working copy)
@@ -67,13 +67,13 @@
# Build the romstage
$(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $(initobjs)
$(obj)/romstage/ldscript.ld
@printf " LINK $(subst $(obj)/,,$(@))\n"
- printf "CONFIG_ROMBASE = 0x0;\n" > $(obj)/location.ld
+ printf "CONFIG_ROMBASE = 0x0;\nAUTO_XIP_ROM_BASE = 0x0;\n" >
$(obj)/location.ld
$(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj)
-T $(obj)/romstage/ldscript.ld $(initobjs)
$(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin
printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld
$(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin
fallback/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt
cat $(obj)/location.txt >> $(obj)/location.ld
- printf ";\n" >> $(obj)/location.ld
+ printf ';\nAUTO_XIP_ROM_BASE = CONFIG_ROMBASE & ~(CONFIG_XIP_ROM_SIZE -
1);\n' >> $(obj)/location.ld
$(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj)
-T $(obj)/romstage/ldscript.ld $(initobjs)
$(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map
$(OBJCOPY) -O binary $(obj)/romstage.elf $@
Index: src/mainboard/kontron/986lcd-m/Kconfig
===================================================================
--- src/mainboard/kontron/986lcd-m/Kconfig (revision 4995)
+++ src/mainboard/kontron/986lcd-m/Kconfig (working copy)
@@ -21,7 +21,7 @@
select IOAPIC
select USE_DCACHE_RAM
select GFXUMA
- select HAVE_MOVNTI
+ select TINY_BOOTBLOCK
config MAINBOARD_DIR
string
@@ -72,8 +72,3 @@
string
default "amipci_01.20"
depends on BOARD_KONTRON_986LCD_M
-
-config HAVE_ACPI_SLIC
- bool
- default n
- depends on BOARD_KONTRON_986LCD_M
Index: src/mainboard/kontron/986lcd-m/Makefile.inc
===================================================================
--- src/mainboard/kontron/986lcd-m/Makefile.inc (revision 4995)
+++ src/mainboard/kontron/986lcd-m/Makefile.inc (working copy)
@@ -40,18 +40,12 @@
initobj-y += crt0.o
# FIXME in $(top)/Makefile
-crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
-crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/arch/i386/lib/id.inc
crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc
crt0-y += auto.inc
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
-ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
-ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/arch/i386/lib/id.lds
-ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds
ifdef POST_EVALUATION
--
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