This patch configures the toppology of rs780 graphics. The new gfx_dual_slot option 2 is for the board which can configure the double/single mode. In that case, we need to know whether a device is plugged behind DEV 3. So the is_dev3_present() is needed. This doesn't help mahogany much. You will need in the future.
Add an option for HDMI display. If you need it, just uncomment it. Signed-off-by: Zheng Bao <[email protected]> Index: src/mainboard/amd/mahogany_fam10/mainboard.c =================================================================== --- src/mainboard/amd/mahogany_fam10/mainboard.c (revision 5223) +++ src/mainboard/amd/mahogany_fam10/mainboard.c (working copy) @@ -35,6 +35,12 @@ uint64_t uma_memory_base, uma_memory_size; +/* This function is stub for mahogany. */ +u8 is_dev3_present() +{ + return 0; +} + /* * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * pull it up before training the slot. Index: src/mainboard/amd/mahogany_fam10/mainboard.c =================================================================== --- src/mainboard/amd/mahogany_fam10/mainboard.c (revision 5223) +++ src/mainboard/amd/mahogany_fam10/mainboard.c (working copy) @@ -35,6 +35,12 @@ uint64_t uma_memory_base, uma_memory_size; +/* This function is stub for mahogany. */ +u8 is_dev3_present() +{ + return 0; +} + /* * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * pull it up before training the slot. Index: src/southbridge/amd/rs780/rs780_gfx.c =================================================================== --- src/southbridge/amd/rs780/rs780_gfx.c (revision 5223) +++ src/southbridge/amd/rs780/rs780_gfx.c (working copy) @@ -37,6 +37,7 @@ void set_pcie_reset(); void set_pcie_dereset(); +u8 is_dev3_present(); #define CLK_CNTL_INDEX 0x8 #define CLK_CNTL_DATA 0xC @@ -430,7 +431,8 @@ //vgainfo.ulSystemConfig |= 1<<1 | 1<<3 | 1<<4 | 1<<5 | 1<<6 | 1<<7 | 1; vgainfo.ulBootUpReqDisplayVector = 0; //? vgainfo.ulOtherDisplayMisc = 0; //? - vgainfo.ulDDISlot1Config = 0x000c0011; //0; //? + vgainfo.ulDDISlot1Config = 0x000c0011; //0; //VGA + //vgainfo.ulDDISlot1Config = 0x000c00FF; //0; //HDMI vgainfo.ulDDISlot2Config = 0x00130022; //0; //? vgainfo.ucMemoryType = 2; /* UMA Channel Number: 1 or 2. */ @@ -989,20 +991,6 @@ /* GFX Core Initialization */ //if (port == 2) return; - /* step 1, lane reversal (only need if CMOS option is enabled) */ - if (cfg->gfx_lane_reversal) { - set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); - if (cfg->gfx_dual_slot) - set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); - } - printk_info("rs780_gfx_init step1.\n"); - - /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ - /* AMD calls the configuration CrossFire */ - if (cfg->gfx_dual_slot) - set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); - printk_info("rs780_gfx_init step2.\n"); - /* step 2, TMDS, (only need if CMOS option is enabled) */ if (cfg->gfx_tmds) { } @@ -1182,11 +1170,70 @@ /* Single-port/Dual-port configureation. */ switch (cfg->gfx_dual_slot) { case 0: - single_port_configuration(nb_dev, dev); + /* step 1, lane reversal (only need if CMOS option is enabled) */ + if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); + } + printk_info("rs780_gfx_init step1.\n"); + printk_info("rs780_gfx_init step2.\n"); + + printk_info("device = %x\n", dev->path.pci.devfn >> 3); + if((dev->path.pci.devfn >> 3) == 2) + single_port_configuration(nb_dev, dev); + else{ + set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */ + printk_info("If dev3.., single port. Do nothing.\n"); + } + break; case 1: + /* step 1, lane reversal (only need if CMOS option is enabled) */ + if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); + } + printk_info("rs780_gfx_init step1.\n"); + /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ + /* AMD calls the configuration CrossFire */ + set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); + printk_info("rs780_gfx_init step2.\n"); + + printk_info("device = %x\n", dev->path.pci.devfn >> 3); dual_port_configuration(nb_dev, dev); break; + /* Some boards are special, the single and dual slots can be configured and + * the graphics behind dev 3 can be detected. */ + case 2: + if(is_dev3_present()){ + /* step 1, lane reversal (only need if CMOS option is enabled) */ + if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); + } + printk_info("rs780_gfx_init step1.\n"); + /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ + /* AMD calls the configuration CrossFire */ + set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); + printk_info("rs780_gfx_init step2.\n"); + + + printk_info("device = %x\n", dev->path.pci.devfn >> 3); + dual_port_configuration(nb_dev, dev); + }else{ + if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); + } + printk_info("rs780_gfx_init step1.\n"); + printk_info("rs780_gfx_init step2.\n"); + + if((dev->path.pci.devfn >> 3) == 2) + single_port_configuration(nb_dev, dev); + else{ + set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */ + printk_info("If dev3.., single port. Do nothing.\n"); + } + } + break; default: printk_info("Incorrect configuration of external gfx slot.\n"); break;
rs780_gfx_config.patch
Description: rs780_gfx_config.patch
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