Author: stepan Date: Wed Mar 17 23:08:51 2010 New Revision: 5253 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5253
Log: revert the faulty part of r5252 Signed-off-by: Stefan Reinauer <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 18:50:48 2010 (r5252) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 23:08:51 2010 (r5253) @@ -177,6 +177,30 @@ pci_write_config16(dev, LPC_EN, 0x300F); } +/* ICH4 does not mention HPET in the docs, but + * all ICH3 and ICH4 do have HPETs built in. + */ +static void enable_hpet(struct device *dev) +{ + u32 reg32; + u32 code = (0 & 0x3); + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (1 << 17); /* Enable HPET. */ + /* + * Bits [16:15] Memory Address Range + * 00 FED0_0000h - FED0_03FFh + * 01 FED0_1000h - FED0_13FFh + * 10 FED0_2000h - FED0_23FFh + * 11 FED0_3000h - FED0_33FFh + */ + reg32 &= ~(3 << 15); /* Clear it */ + reg32 |= (code << 15); + pci_write_config32(dev, GEN_CNTL, reg32); + + printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); +} + static void lpc_init(struct device *dev) { /* Set the value for PCI command register. */ @@ -207,6 +231,9 @@ /* Setup decode ports and LPC I/F enables. */ i82801dx_lpc_decode_en(dev); + + /* Initialize the High Precision Event Timers */ + enable_hpet(dev); } static void i82801dx_lpc_read_resources(device_t dev) -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
