Author: stepan Date: Wed Mar 17 23:09:26 2010 New Revision: 5254 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5254
Log: more warnings gone... Signed-off-by: Stefan Reinauer <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/src/cpu/amd/model_lx/vsmsetup.c trunk/src/northbridge/amd/lx/northbridge.c trunk/src/northbridge/amd/lx/northbridgeinit.c trunk/src/northbridge/amd/lx/raminit.c trunk/src/southbridge/amd/cs5536/cs5536.c trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c trunk/src/southbridge/amd/sb600/sb600_hda.c trunk/src/southbridge/amd/sb600/sb600_sata.c trunk/src/southbridge/amd/sb600/sb600_usb.c trunk/src/southbridge/amd/sb700/sb700_hda.c trunk/src/southbridge/amd/sb700/sb700_usb.c Modified: trunk/src/cpu/amd/model_lx/vsmsetup.c ============================================================================== --- trunk/src/cpu/amd/model_lx/vsmsetup.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/cpu/amd/model_lx/vsmsetup.c Wed Mar 17 23:09:26 2010 (r5254) @@ -290,7 +290,7 @@ if ((unsigned int)cbfs_load_stage("vsa") != VSA2_ENTRY_POINT) { printk_err("do_vsmbios: Failed to load VSA.\n"); } - buf = VSA2_BUFFER; + buf = (unsigned char *)VSA2_BUFFER; printk_debug("buf %p *buf %d buf[256k] %d\n", buf, buf[0], buf[SMM_SIZE * 1024]); printk_debug("buf[0x20] signature is %x:%x:%x:%x\n", @@ -501,15 +501,15 @@ printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n", ebp, esp, edi, esi); printk_debug("biosint: ip 0x%x cs 0x%x flags 0x%x\n", - ip, cs, flags); + (u32)ip, (u32)cs, (u32)flags); printk_debug("biosint: gs 0x%x fs 0x%x ds 0x%x es 0x%x\n", - gsfs >> 16, gsfs & 0xffff, dses >> 16, dses & 0xffff); + (u16)(gsfs >> 16), (u16)(gsfs & 0xffff), (u16)(dses >> 16), (u16)(dses & 0xffff)); // cases in a good compiler are just as good as your own tables. switch (intnumber) { case 0 ... 15: // These are not BIOS service, but the CPU-generated exceptions - printk_info("biosint: Oops, exception %u\n", intnumber); + printk_info("biosint: Oops, exception 0x%x\n", (u32)intnumber); if (esp < 0x1000) { printk_debug("Stack contents: "); while (esp < 0x1000) { @@ -537,7 +537,7 @@ &ebx, &edx, &ecx, &eax, &flags); break; default: - printk_info("BIOSINT: Unsupport int #0x%x\n", intnumber); + printk_info("BIOSINT: Unsupported int #0x%x\n", (u32)intnumber); break; } if (ret) @@ -617,16 +617,7 @@ unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, unsigned long *pecx, unsigned long *peax, unsigned long *pflags) { - unsigned long edi = *pedi; - unsigned long esi = *pesi; - unsigned long ebp = *pebp; - unsigned long esp = *pesp; - unsigned long ebx = *pebx; - unsigned long edx = *pedx; - unsigned long ecx = *pecx; - unsigned long eax = *peax; - unsigned long flags = *pflags; - unsigned short func = (unsigned short)eax; + unsigned short func = (unsigned short)*peax; int retval = 0; unsigned short devid, vendorid, devfn; short devindex; /* Use short to get rid of gabage in upper half of 32-bit register */ @@ -740,7 +731,7 @@ unsigned long *ecx, unsigned long *eax, unsigned long *flags) { int res = -1; - printk_debug("handleint21, eax 0x%x\n", *eax); + printk_debug("handleint21, eax 0x%x\n", (u32)*eax); switch (*eax & 0xffff) { case 0x5f19: break; Modified: trunk/src/northbridge/amd/lx/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/lx/northbridge.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/northbridge/amd/lx/northbridge.c Wed Mar 17 23:09:26 2010 (r5254) @@ -253,16 +253,16 @@ } iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE); - printk_debug("IOR 0x%08X is now 0x%08X\n", + printk_debug("IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol); iol = inl(GPIOL_EVENTS_ENABLE); - printk_debug("IOR 0x%08X is now 0x%08X\n", + printk_debug("IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol); iol = inl(GPIOL_INPUT_INVERT_ENABLE); - printk_debug("IOR 0x%08X is now 0x%08X\n", + printk_debug("IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol); iol = inl(GPIO_MAPPER_X); - printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X, + printk_debug("IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X, iol); #endif //CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR } Modified: trunk/src/northbridge/amd/lx/northbridgeinit.c ============================================================================== --- trunk/src/northbridge/amd/lx/northbridgeinit.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/northbridge/amd/lx/northbridgeinit.c Wed Mar 17 23:09:26 2010 (r5254) @@ -107,7 +107,7 @@ msr.lo = gl->lo; msr.hi = gl->hi; wrmsr(gl->desc_name, msr); // MSR - see table above - printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); // GX3 + printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); // GX3 } static void ShadowInit(struct gliutable *gl) @@ -147,7 +147,7 @@ msr.lo = sizebytes; wrmsr(gl->desc_name, msr); // MSR - see table above - printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __func__, + printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } @@ -173,7 +173,7 @@ msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff; wrmsr(gl->desc_name, msr); // MSR - See table above - printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __func__, + printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } @@ -190,7 +190,7 @@ msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff; wrmsr(gl->desc_name, msr); // MSR - See table above - printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __func__, + printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } Modified: trunk/src/northbridge/amd/lx/raminit.c ============================================================================== --- trunk/src/northbridge/amd/lx/raminit.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/northbridge/amd/lx/raminit.c Wed Mar 17 23:09:26 2010 (r5254) @@ -27,12 +27,13 @@ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F }; -void banner(char *s) +void banner(const char *s) { print_debug("==========================="); print_debug(s); print_debug("======================================\r\n"); } + void hcf(void) { print_emerg("DIE\r\n"); Modified: trunk/src/southbridge/amd/cs5536/cs5536.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/southbridge/amd/cs5536/cs5536.c Wed Mar 17 23:09:26 2010 (r5254) @@ -35,7 +35,7 @@ #include "cs5536.h" struct msrinit { - uint32_t msrnum; + u32 msrnum; msr_t msr; }; @@ -61,8 +61,8 @@ }; struct acpiinit { - uint16_t ioreg; - uint32_t regdata; + u16 ioreg; + u32 regdata; }; struct acpiinit acpi_init_table[] = { @@ -95,7 +95,7 @@ #define FlashInitTableLen (ARRAY_SIZE(FlashInitTable)) -uint32_t FlashPort[] = { +u32 FlashPort[] = { MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LBAR_FLSH2, @@ -111,8 +111,8 @@ /* ***************************************************************************/ static void pmChipsetInit(void) { - uint32_t val = 0; - uint16_t port; + u32 val = 0; + u16 port; port = (PMS_IO_BASE + 0x010); val = 0x0E00; /* 1ms */ @@ -427,7 +427,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) { - uint8_t *bar; + u32 bar; msr_t msr; device_t dev; @@ -443,7 +443,7 @@ /* write to clear diag register */ wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG)); - bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); /* Make HCCPARAMS writeable */ write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET); @@ -455,7 +455,7 @@ dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); if (dev) { - bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET); @@ -483,8 +483,7 @@ dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); if (dev) { - bar = (uint8_t *) pci_read_config32(dev, - PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); write32(bar + UDCDEVCTL, read32(bar + UDCDEVCTL) | UDC_SD_SET); @@ -493,8 +492,7 @@ dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); if (dev) { - bar = (uint8_t *) pci_read_config32(dev, - PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET); write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET); } @@ -524,7 +522,7 @@ { device_t dev; msr_t msr; - uint32_t msrnum; + u32 msrnum; struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info; struct msrinit *csi; Modified: trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Wed Mar 17 23:09:26 2010 (r5254) @@ -32,13 +32,11 @@ /* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */ msr.hi = msr.lo = 0x00000000; - if (CS5536_GLINK_PORT_NUM <= 4) { - msr.lo = CS5536_DEV_NUM << - (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8); - } else { - msr.hi = CS5536_DEV_NUM << - (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8); - } +#if CS5536_GLINK_PORT_NUM <= 4 + msr.lo = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8); +#else + msr.hi = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8); +#endif wrmsr(GLPCI_ExtMSR, msr); } Modified: trunk/src/southbridge/amd/sb600/sb600_hda.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_hda.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/southbridge/amd/sb600/sb600_hda.c Wed Mar 17 23:09:26 2010 (r5254) @@ -30,7 +30,7 @@ #define HDA_ICII_BUSY (1 << 0) #define HDA_ICII_VALID (1 << 1) -static int set_bits(u8 * port, u32 mask, u32 val) +static int set_bits(u32 port, u32 mask, u32 val) { u32 dword; int count; @@ -59,7 +59,7 @@ return 0; } -static u32 codec_detect(u8 * base) +static u32 codec_detect(u32 base) { u32 dword; @@ -172,7 +172,7 @@ * no response would imply that the codec is non-operative */ -static int wait_for_ready(u8 *base) +static int wait_for_ready(u32 base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -195,7 +195,7 @@ * is non-operative */ -static int wait_for_valid(u8 *base) +static int wait_for_valid(u32 base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -212,7 +212,7 @@ return 1; } -static void codec_init(u8 * base, int addr) +static void codec_init(u32 base, int addr) { u32 dword; u32 *verb; @@ -254,7 +254,7 @@ printk_debug("verb loaded!\n"); } -static void codecs_init(u8 * base, u32 codec_mask) +static void codecs_init(u32 base, u32 codec_mask) { int i; for (i = 2; i >= 0; i--) { @@ -267,7 +267,7 @@ { u8 byte; u32 dword; - u8 *base; + u32 base; struct resource *res; u32 codec_mask; device_t sm_dev; @@ -301,8 +301,8 @@ if (!res) return; - base = (u8 *) ((u32)res->base); - printk_debug("base = %p\n", base); + base = ((u32)res->base); + printk_debug("base = 0x%x\n", base); codec_mask = codec_detect(base); if (codec_mask) { Modified: trunk/src/southbridge/amd/sb600/sb600_sata.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_sata.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/southbridge/amd/sb600/sb600_sata.c Wed Mar 17 23:09:26 2010 (r5254) @@ -27,7 +27,7 @@ #include <arch/io.h> #include "sb600.h" -int sata_drive_detect(int portnum, u16 iobar) +static int sata_drive_detect(int portnum, u16 iobar) { u8 byte, byte2; int i = 0; @@ -59,7 +59,7 @@ u8 byte; u16 word; u32 dword; - u8 *sata_bar5; + u32 sata_bar5; u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; int i, j; @@ -84,7 +84,7 @@ pci_write_config8(sm_dev, 0xaf, byte); /* get base addresss */ - sata_bar5 = (u8 *) (pci_read_config32(dev, 0x24) & ~0x3FF); + sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF; sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7; @@ -96,7 +96,7 @@ printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */ printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */ printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */ - printk_spew("sata_bar5=%p\n", sata_bar5); /* e0309000 */ + printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */ /* Program the 2C to 0x43801002 */ dword = 0x43801002; Modified: trunk/src/southbridge/amd/sb600/sb600_usb.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_usb.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/southbridge/amd/sb600/sb600_usb.c Wed Mar 17 23:09:26 2010 (r5254) @@ -88,13 +88,13 @@ u8 byte; u16 word; u32 dword; - u8 *usb2_bar0; + u32 usb2_bar0; /* dword = pci_read_config32(dev, 0xf8); */ /* dword |= 40; */ /* pci_write_config32(dev, 0xf8, dword); */ - usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF); - printk_info("usb2_bar0=%p\n", usb2_bar0); + usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; + printk_info("usb2_bar0=0x%x\n", usb2_bar0); /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; Modified: trunk/src/southbridge/amd/sb700/sb700_hda.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_hda.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/southbridge/amd/sb700/sb700_hda.c Wed Mar 17 23:09:26 2010 (r5254) @@ -30,7 +30,7 @@ #define HDA_ICII_BUSY (1 << 0) #define HDA_ICII_VALID (1 << 1) -static int set_bits(u8 * port, u32 mask, u32 val) +static int set_bits(u32 port, u32 mask, u32 val) { u32 dword; int count; @@ -59,7 +59,7 @@ return 0; } -static u32 codec_detect(u8 * base) +static u32 codec_detect(u32 base) { u32 dword; @@ -94,7 +94,7 @@ * Wait 50usec for for the codec to indicate it is ready * no response would imply that the codec is non-operative */ -static int wait_for_ready(u8 *base) +static int wait_for_ready(u32 base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -116,7 +116,7 @@ * the previous command. No response would imply that the code * is non-operative */ -static int wait_for_valid(u8 *base) +static int wait_for_valid(u32 base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -133,7 +133,7 @@ return 1; } -static void codec_init(u8 * base, int addr) +static void codec_init(u32 base, int addr) { u32 dword; @@ -153,7 +153,7 @@ printk_debug("%x(th) codec viddid: %08x\n", addr, dword); } -static void codecs_init(u8 * base, u32 codec_mask) +static void codecs_init(u32 base, u32 codec_mask) { int i; for (i = 2; i >= 0; i--) { @@ -166,7 +166,7 @@ { u8 byte; u32 dword; - u8 *base; + u32 base; struct resource *res; u32 codec_mask; device_t sm_dev; @@ -202,8 +202,8 @@ if (!res) return; - base = (u8 *) ((u32)res->base); - printk_debug("base = %p\n", base); + base = (u32)res->base; + printk_debug("base = 0x%x\n", base); codec_mask = codec_detect(base); if (codec_mask) { Modified: trunk/src/southbridge/amd/sb700/sb700_usb.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_usb.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/southbridge/amd/sb700/sb700_usb.c Wed Mar 17 23:09:26 2010 (r5254) @@ -34,7 +34,6 @@ { u8 byte; u16 word; - u32 dword; /* 6.1 Enable OHCI0-4 and EHCI Controllers */ device_t sm_dev; @@ -70,10 +69,8 @@ static void usb_init2(struct device *dev) { - u8 byte; - u16 word; u32 dword; - u8 *usb2_bar0; + u32 usb2_bar0; device_t sm_dev; u8 rev; @@ -84,8 +81,8 @@ /* dword |= 40; */ /* pci_write_config32(dev, 0xf8, dword); */ - usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF); - printk_info("usb2_bar0=%p\n", usb2_bar0); + usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; + printk_info("usb2_bar0=0x%x\n", usb2_bar0); /* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; @@ -123,6 +120,9 @@ /* Each step below causes the linux crashes. Leave them here * for future debugging. */ #if 0 + u8 byte; + u16 word; + /* RPR6.16 Disable EHCI MSI support */ byte = pci_read_config8(dev, 0x50); byte |= (1 << 6); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
