Am 26.03.2010 20:25, schrieb Stefan Reinauer: > What information would be in those SSDTs if they were there? > > On i945 we only generate one SSDT for the CPU frequency scaling code, > but it isn't compiled through iasl, so no AmlCode hacks. > If the code is there at compile time (which it has to be when using > iasl) then it could as well be included in the dsdt. > > Just want to make sure we erase people's S-ATA config or so by accident.. The AMD code seems to select the "right" SSDT on runtime, or something similarily arcane.
Patrick -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
