hi all,
i was to fast on the send button, the Nokia IP530 is now finally fully
working.
- the four on-board NICs (22143PD)
- the 2 PCMCIA-Cardbus slots
- the 3 compact PCI expansion slots (with 12 NICs)
I got it working with 16 ethernet controller (all 21143PD), two HDDs on
the primary IDE controller and two HDD's on the secondary controller.
The on-board CF slot works as master on the primary IDE controller. very
nice for silent running (hihi, with those 4 fan's in the back).
for the NICs i added a driver to the src/drivers/dec/21143. for the
pcmcia-cardbus controller i added a driver to the
src/drivers/ti/pcmcia-cardbus. these where required to get the devices
proberly working. These are added as drivers so that other can use then
in there configuration to. the parameters can be set in the
configuration "menuconfig", "xconfig" or "gconfig".
all this depends still on a patch to the
'src/arch/i386/boot/pirq_routing.c' to get the interrupt routing correct
working. i will look into this to fix in the near future.
I find the coreboot project a great project and i have a lot of fun
working on it. and i will do so. Next on mylist is the Nokia-IP330, yes
again a Nokia piece of hardware.
"That's all folks"
Marc
Index: src/arch/i386/boot/pirq_routing.c
===================================================================
--- src/arch/i386/boot/pirq_routing.c (revision 5600)
+++ src/arch/i386/boot/pirq_routing.c (working copy)
@@ -1,3 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000-2010 Coreboot project
+ * Copyright (C) 2010 Marc Bertens <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
#include <console/console.h>
#include <arch/pirq_routing.h>
#include <string.h>
@@ -64,7 +84,7 @@
rt_curr = (uint8_t*)addr;
rt_orig = (uint8_t*)&intel_irq_routing_table;
- printk(BIOS_INFO, "Verifing copy of Interrupt Routing Table at 0x%08x... ", addr);
+ printk(BIOS_INFO, "Verifing copy of Interrupt Routing Table at 0x%08lx... ", addr);
for (i = 0; i < intel_irq_routing_table.size; i++) {
if (*(rt_curr + i) != *(rt_orig + i)) {
printk(BIOS_INFO, "failed\n");
@@ -121,7 +141,17 @@
printk(BIOS_DEBUG, "INT: %c link: %x bitmap: %x ",
'A' + j, link, bitmap);
-
+#if CONFIG_BOARD_NOKIA_IP530
+ /**
+ * TODO: this was done for the Northbridge i440BX, due to
+ * the fact that the values in the PIRQ table needs to be
+ * 60, 61, 62 and 63. Fixing this needs some investigating
+ * and fixes at other points in de code.
+ */
+ if (link > 0x5f) {
+ link -= 0x5f;
+ }
+#endif
if (!bitmap|| !link || link > 4) {
printk(BIOS_DEBUG, "not routed\n");
Index: src/include/device/pci_ids.h
===================================================================
--- src/include/device/pci_ids.h (revision 5600)
+++ src/include/device/pci_ids.h (working copy)
@@ -696,6 +696,7 @@
#define PCI_DEVICE_ID_TI_4410 0xac41
#define PCI_DEVICE_ID_TI_4451 0xac42
#define PCI_DEVICE_ID_TI_1420 0xac51
+#define PCI_DEVICE_ID_TI_1520 0xAC55
#define PCI_VENDOR_ID_SONY 0x104d
#define PCI_DEVICE_ID_SONY_CXD3222 0x8039
@@ -1741,6 +1742,10 @@
#define PCI_DEVICE_ID_CCD_B00C 0xb00c
#define PCI_DEVICE_ID_CCD_B100 0xb100
+#define PCI_VENDOR_ID_NOKIA 0x13B8 // Nokia Telecommunications oy
+#define PCI_VENDOR_ID_NOKIA_WIRELESS 0x1603 // Nokia Wireless Communications
+#define PCI_VENDOR_ID_NOKIA_HOME 0x1622 // Nokia Home Communications
+
#define PCI_VENDOR_ID_3WARE 0x13C1
#define PCI_DEVICE_ID_3WARE_1000 0x1000
Index: src/drivers/Kconfig
===================================================================
--- src/drivers/Kconfig (revision 5600)
+++ src/drivers/Kconfig (working copy)
@@ -23,3 +23,21 @@
help
It sets PCI class to IDE compatible native mode, allowing
SeaBIOS, FILO etc... to boot from it.
+
+config DRIVERS_TI
+ bool "Texas Instruments PCMCIA/CardBus controller"
+ default n
+ help
+ Enables the PCI1225, 1420 and 1520 drivers. This driver
+ (PCI1225) is developed and needed for the NOKIA IP530.
+
+source src/drivers/ti/Kconfig
+
+config DRIVERS_DEC21143PD
+ bool "21143 PCI/CardBus 10/100 Mb/s Ethernet LAN Controller"
+ default n
+ help
+ Enables the DEC21143PD driver. This driver is developed
+ and needed for the NOKIA IP530.
+
+source src/drivers/dec/Kconfig
Index: src/drivers/Makefile.inc
===================================================================
--- src/drivers/Makefile.inc (revision 5600)
+++ src/drivers/Makefile.inc (working copy)
@@ -1,3 +1,5 @@
subdirs-y += generic/debug
subdirs-y += ati/ragexl
subdirs-y += sil/3114
+subdirs-y += ti/pcmcia-cardbus
+subdirs-y += dec/21143
Index: src/drivers/dec/Kconfig
===================================================================
--- src/drivers/dec/Kconfig (revision 0)
+++ src/drivers/dec/Kconfig (revision 0)
@@ -0,0 +1,25 @@
+menu "Dec 21143 PCI/CardBus 10/100-Mb/s Ethernet LAN Controller"
+ depends on DRIVERS_DEC21143PD
+
+config DEC21143_CACHE_LINE_SIZE
+ hex "Cache Line Size Register"
+ default 0x00000000
+ help
+ Corrects the 'Cache Line Size Register' to a initial value,
+ when not sure set value to 0.
+
+config DEC21143_EXPANSION_ROM_BASE_ADDRESS
+ hex "Expansion ROM Base Address"
+ default 0
+ help
+ Sets the 'Expansion ROM Base Address' for the controller, when
+ not sure set value 0.
+
+config DEC21143_COMMAND_AND_STATUS_CONFIGURATION
+ hex "Command and Status Configuration"
+ default 0x02800107
+ help
+ Set the 'Command and Status Configuration', when not sure
+ set 0x02800107 or 0x02800007
+
+endmenu
Index: src/drivers/dec/21143/21143pd.c
===================================================================
--- src/drivers/dec/21143/21143pd.c (revision 0)
+++ src/drivers/dec/21143/21143pd.c (revision 0)
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+
+/**
+ * This driver take the values from Kconfig and load them in the registers
+ */
+static void dec_21143pd_enable( device_t dev )
+{
+ printk( BIOS_DEBUG, "Init of DECchip 21143PD/TD Kconfig style\n");
+ // Command and Status Configuration Register (CFCS–Offset 04H)
+ pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION );
+ printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) );
+ // Cache Line Size Register (Offset 0x0C)
+ pci_write_config8( dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE );
+ printk( BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", pci_read_config32(dev, 0x0C) );
+ // Expansion ROM Base Address Register (CBER–Offset 30H)
+ pci_write_config32( dev, 0x30, CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS );
+ printk( BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", pci_read_config32(dev, 0x30) );
+ return;
+}
+
+static struct device_operations dec_21143pd_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = dec_21143pd_enable,
+ .scan_bus = 0,
+};
+
+static const struct pci_driver dec_21143pd_driver __pci_driver = {
+ .ops = &dec_21143pd_ops,
+ .vendor = PCI_VENDOR_ID_DEC,
+ .device = PCI_DEVICE_ID_DEC_21142,
+};
Index: src/drivers/dec/21143/Makefile.inc
===================================================================
--- src/drivers/dec/21143/Makefile.inc (revision 0)
+++ src/drivers/dec/21143/Makefile.inc (revision 0)
@@ -0,0 +1,5 @@
+##
+## Each chip needs the generic file and a specific file
+##
+driver-$(CONFIG_DRIVERS_DEC21143PD) += 21143pd.o
+
Index: src/drivers/ti/Kconfig
===================================================================
--- src/drivers/ti/Kconfig (revision 0)
+++ src/drivers/ti/Kconfig (revision 0)
@@ -0,0 +1,22 @@
+menu "Texas Instruments PCMCIA/CardBus controller support"
+ depends on DRIVERS_TI
+
+config PCI1225
+ bool "Texas Instruments PCI1225 PCMCIA/CardBus controller"
+ default n
+ help
+ Enables the PCI1225 PCMCIA/CardBus controller
+
+config PCI1420
+ bool "Texas Instruments PCI1420 PCMCIA/CardBus controller"
+ default n
+ help
+ Enables the PCI1420 PCMCIA/CardBus controller
+
+config PCI1520
+ bool "Texas Instruments PCI1520 PCMCIA/CardBus controller"
+ default n
+ help
+ Enables the PCI1520 PCMCIA/CardBus controller
+
+endmenu
Index: src/drivers/ti/pcmcia-cardbus/pci1420.c
===================================================================
--- src/drivers/ti/pcmcia-cardbus/pci1420.c (revision 0)
+++ src/drivers/ti/pcmcia-cardbus/pci1420.c (revision 0)
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+ #include "ti-pcmcia-cardbus.h"
+/**
+ * This is the specific implenetation for the PCI1420 PCMCIA/CardBus controler
+ * the ti_pci1x2y_init() function located in 'ti-pcmcia-cardbus.c'
+ */
+
+static struct device_operations ti_pci1420_ops = {
+ .read_resources = NULL, // pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = ti_pci1x2y_init,
+ .scan_bus = 0,
+};
+
+static const struct pci_driver ti_pci1420_driver __pci_driver = {
+ .ops = &ti_pci1420_ops,
+ .vendor = PCI_VENDOR_ID_TI,
+ .device = PCI_DEVICE_ID_TI_1420,
+};
+
Index: src/drivers/ti/pcmcia-cardbus/pci1520.c
===================================================================
--- src/drivers/ti/pcmcia-cardbus/pci1520.c (revision 0)
+++ src/drivers/ti/pcmcia-cardbus/pci1520.c (revision 0)
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include "ti-pcmcia-cardbus.h"
+/**
+ * This is the specific implenetation for the PCI1420 PCMCIA/CardBus controler
+ * the ti_pci1x2y_init() function located in 'ti-pcmcia-cardbus.c'
+ */
+
+static struct device_operations ti_pci1520_ops = {
+ .read_resources = NULL, // pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = ti_pci1x2y_init,
+ .scan_bus = 0,
+};
+
+static const struct pci_driver ti_pci1520_driver __pci_driver = {
+ .ops = &ti_pci1520_ops,
+ .vendor = PCI_VENDOR_ID_TI,
+ .device = PCI_DEVICE_ID_TI_1420,
+};
+
Index: src/drivers/ti/pcmcia-cardbus/Makefile.inc
===================================================================
--- src/drivers/ti/pcmcia-cardbus/Makefile.inc (revision 0)
+++ src/drivers/ti/pcmcia-cardbus/Makefile.inc (revision 0)
@@ -0,0 +1,8 @@
+##
+## Each chip needs the generic file and a specific file
+##
+driver-$(CONFIG_DRIVERS_TI) += ti-pcmcia-cardbus.o
+driver-$(CONFIG_PCI1225) += pci1225.o
+driver-$(CONFIG_PCI1420) += pci1420.o
+driver-$(CONFIG_PCI1520) += pci1520.o
+
Index: src/drivers/ti/pcmcia-cardbus/pci1225.c
===================================================================
--- src/drivers/ti/pcmcia-cardbus/pci1225.c (revision 0)
+++ src/drivers/ti/pcmcia-cardbus/pci1225.c (revision 0)
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include "ti-pcmcia-cardbus.h"
+/**
+ * This is the specific implenetation for the PCI1225 PCMCIA/CardBus controler
+ * the ti_pci1x2y_init() function located in 'ti-pcmcia-cardbus.c'
+ */
+
+static struct device_operations ti_pci1225_ops = {
+ .read_resources = NULL, //pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = ti_pci1x2y_init,
+ .scan_bus = 0,
+};
+
+static const struct pci_driver ti_pci1225_driver __pci_driver = {
+ .ops = &ti_pci1225_ops,
+ .vendor = PCI_VENDOR_ID_TI,
+ .device = PCI_DEVICE_ID_TI_1225,
+};
+
Index: src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c
===================================================================
--- src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c (revision 0)
+++ src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c (revision 0)
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include "ti-pcmcia-cardbus.h"
+/**
+ * This is the general PCMCIA/CardBus controller setup
+ * the following devices are supported by this PCI1225, PCI1420 and
+ * the PCI1520.
+ * The implementation is taken from the PCI1520 implementation Guide
+ * For each chip there is a specific file to handle the identification.
+ */
+
+#define CONFIG_TI_PCMCIA_CARDBUS_CMDR 0x0107
+#define CONFIG_TI_PCMCIA_CARDBUS_CLSR 0x00
+#define CONFIG_TI_PCMCIA_CARDBUS_CLTR 0x40
+#define CONFIG_TI_PCMCIA_CARDBUS_BCR 0x07C0
+#define CONFIG_TI_PCMCIA_CARDBUS_SCR 0x08449060
+#define CONFIG_TI_PCMCIA_CARDBUS_MRR 0x00007522
+
+void ti_pci1x2y_init(struct device *dev)
+{
+ printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
+ // Command register (offset 04)
+ pci_write_config16( dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR );
+ // Cache Line Size Register (offset 0x0C) will be set to zero, i assume no cache
+ pci_write_config8( dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR );
+ // CardBus latency timer register (offset 1B)
+ pci_write_config8( dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR );
+ // Bridge control register (offset 3E)
+ pci_write_config16( dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR );
+ /** Enable change sub-vendor id
+ * Clear the bit 5 to enable to write to the sub-vendor/device ids at 40 and 42 */
+ pci_write_config32( dev, 0x80, 0x10 );
+ pci_write_config32( dev, 0x40, PCI_VENDOR_ID_NOKIA );
+ // Now write the correct value for SCR
+ // System Control Register (offset 0x80) will be set to the value 0x00224010.
+ pci_write_config32( dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR );
+ // Multifunction routing register
+ pci_write_config32( dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR );
+ // Set Device Control Register (0x92) accordingly
+ pci_write_config8( dev, 0x92, pci_read_config8( dev, 0x92 ) | 0x02 );
+ return;
+}
Index: src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.h
===================================================================
--- src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.h (revision 0)
+++ src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.h (revision 0)
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#ifndef __TI_PCMCIA_CARDBUS_H__
+#define __TI_PCMCIA_CARDBUS_H__
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+
+void ti_pci1x2y_init(struct device *dev);
+
+#endif
Index: src/mainboard/nokia/ip530/Kconfig
===================================================================
--- src/mainboard/nokia/ip530/Kconfig (revision 5600)
+++ src/mainboard/nokia/ip530/Kconfig (working copy)
@@ -25,9 +25,9 @@
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_SMSC_SMSCSUPERIO
select ROMCC
- select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select GENERATE_PIRQ_TABLE
select UDELAY_TSC
- select BOARD_ROMSIZE_KB_256
config MAINBOARD_DIR
string
@@ -46,6 +46,6 @@
config IRQ_SLOT_COUNT
int
- default 6
+ default 22
depends on BOARD_NOKIA_IP530
Index: src/mainboard/nokia/ip530/devicetree.cb
===================================================================
--- src/mainboard/nokia/ip530/devicetree.cb (revision 5600)
+++ src/mainboard/nokia/ip530/devicetree.cb (working copy)
@@ -1,5 +1,6 @@
##
## This file is part of the coreboot project.
+## This is the device tree for a Nokia IP530.
##
## Copyright (C) 2010 Marc Bertens <[email protected]>
##
@@ -17,78 +18,56 @@
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-
-chip northbridge/intel/i440bx # Northbridge
- device lapic_cluster 0 on # APIC cluster
- chip cpu/intel/socket_PGA370 # CPU
- device lapic 0 on end # APIC
- end
- end
- device pci_domain 0 on # PCI domain
- device pci 0.0 on end # Host bridge
- device pci 1.0 on end # PCI/AGP bridge
- chip southbridge/intel/i82371eb # Southbridge
- device pci 7.0 on # ISA bridge
- chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37C878)
- device pnp 3f0.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 3f0.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 4
- end
- device pnp 3f0.4 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 3f0.5 on # COM2 / IR
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 3f0.7 on # PS/2 keyboard / mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # PS/2 keyboard interrupt
- irq 0x72 = 12 # PS/2 mouse interrupt
- end
- device pnp 3f0.9 on # Game port
- io 0x60 = 0x201
- end
- device pnp 3f0.a on # Power-management events (PME)
- io 0x60 = 0x600
- end
- device pnp 3f0.b on # MIDI port (MPU-401)
- io 0x60 = 0x330
- irq 0x70 = 5
- end
- end
- end
- device pci 7.1 on end # IDE
- device pci 7.2 on end # USB
- device pci 7.3 on end # ACPI
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "ide_legacy_enable" = "1"
- # Enable UDMA/33 for higher speed if your IDE device(s) support it.
- register "ide0_drive0_udma33_enable" = "0"
- register "ide0_drive1_udma33_enable" = "0"
- register "ide1_drive0_udma33_enable" = "0"
- register "ide1_drive1_udma33_enable" = "0"
- end
- device pci 0d.0 on end # NIC (DEC DECchip 21142/43)
- device pci 0e.0 on end # NIC (DEC DECchip 21142/43)
- device pci 0f.0 on end # CardBus bridge (TI PCI1225)
- device pci 0f.1 on end # CardBus bridge (TI PCI1225)
- end
- device pci_domain 1 on # PCI domain 1
- device pci 00.0 on end # PCI bridge (DEC DECchip 21150)
- end
- device pci_domain 2 on # PCI domain 2
- device pci 04.0 on end # NIC (DECchip 21142/43)
- device pci 04.0 on end # NIC (DECchip 21142/43)
- end
+chip northbridge/intel/i440bx # Northbridge
+ device lapic_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_PGA370 # CPU
+ device lapic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Host bridge
+ device pci 1.0 on end # PCI/AGP bridge
+ chip southbridge/intel/i82371eb # Southbridge
+ device pci 7.0 on # ISA bridge
+ chip superio/smsc/smscsuperio # Super I/O FDC 37C878
+ # There is no connector for the Floppy
+ # is on the board the FDD controller is
+ # disabled.
+ device pnp 3f0.0 off end # Floppy
+ # There is no connector for the LPT
+ # device is on the board the LPT
+ # controller is disabled.
+ device pnp 3f0.3 off end # Parallel port
+ device pnp 3f0.4 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 3f0.5 on # COM2 / IR
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 3f0.7 on end # PS/2 keyboard / mouse
+ device pnp 3f0.6 on end # RTC
+ device pnp 3f0.8 on end # AUX I/O
+ # There is no ACPI support for this
+ # board, therefor its disabled.
+ device pnp 3f0.A off end # ACPI
+ end
+ end
+ device pci 7.1 on end # IDE
+ # There is no USB connector therefor its disabled
+ device pci 7.2 off end # USB
+ # There is no ACPI support for this board
+ # so ACPI is disabled.
+ device pci 7.3 off end # ACPI
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "ide_legacy_enable" = "1"
+ # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+ register "ide0_drive0_udma33_enable" = "1"
+ register "ide0_drive1_udma33_enable" = "1"
+ register "ide1_drive0_udma33_enable" = "1"
+ register "ide1_drive1_udma33_enable" = "1"
+ end
+ end
end
-
Index: src/mainboard/nokia/ip530/irq_tables.c
===================================================================
--- src/mainboard/nokia/ip530/irq_tables.c (revision 5600)
+++ src/mainboard/nokia/ip530/irq_tables.c (working copy)
@@ -31,15 +31,46 @@
0x122e, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x36, /* Checksum */
+ 0x44, /* Checksum */
{
- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x07 << 3) | 0x0, {{0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x63, 0x0ea8}}, 0x0, 0x0},
- {0x00, (0x0c << 3) | 0x0, {{0x61, 0x06a8}, {0x62, 0x06a8}, {0x00, 0x06a8}, {0x00, 0x06a8}}, 0x0, 0x0},
- {0x00, (0x0d << 3) | 0x0, {{0x60, 0x0ea8}, {0x61, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x1, 0x0},
- {0x00, (0x09 << 3) | 0x0, {{0x62, 0x0ea8}, {0x63, 0x0ea8}, {0x60, 0x0ea8}, {0x61, 0x0ea8}}, 0x2, 0x0},
- {0x00, (0x0a << 3) | 0x0, {{0x63, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
- {0x01, (0x00 << 3) | 0x0, {{0x60, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
+ /**
+ * Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller.
+ */
+ // Southbridge 82371
+ { 0x00, (0x07 << 3) | 0x0, {{0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 },
+ // On-board PCI-to-PCI bridge
+ { 0x01, (0x00 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 },
+ // ETH1 on front panel
+ { 0x00, (0x0d << 3) | 0x0, {{0x62, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+ // ETH2 on front panel
+ { 0x00, (0x0e << 3) | 0x0, {{0x63, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+ // ETH3 on front panel
+ { 0x02, (0x04 << 3) | 0x0, {{0x60, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+ // ETH4 on front panel
+ { 0x02, (0x05 << 3) | 0x0, {{0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+ // PCMCIA/Cardbus controller
+ { 0x00, (0x0f << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+ // Bridge for slot 1 (top)
+ { 0x02, (0x07 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x64, 0x1E20}}, 0x0, 0x0 },
+ // PCI compact slots 1 (top)
+ { 0x03, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x1, 0x0 },
+ { 0x03, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x2, 0x0 },
+ { 0x03, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x3, 0x0 },
+ { 0x03, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x4, 0x0 },
+ // Bridge for slot 2 (middle)
+ { 0x02, (0x06 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 },
+ // PCI compact slots 2 (middle)
+ { 0x04, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x5, 0x0 },
+ { 0x04, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x6, 0x0 },
+ { 0x04, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x7, 0x0 },
+ { 0x04, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x8, 0x0 },
+ // Bridge for slot 3 (bottom)
+ { 0x00, (0x10 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 },
+ // PCI compact slots 3 (bottom)
+ { 0x05, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x9, 0x0 },
+ { 0x05, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0xA, 0x0 },
+ { 0x05, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0xB, 0x0 },
+ { 0x05, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0xC, 0x0 },
}
};
@@ -47,3 +78,13 @@
{
return copy_pirq_routing_table(addr);
}
+
+/**
+ * TODO: This stub function is here until the point is solved in the
+ * main code of coreboot. see also arch/i386/boot/pirq_tables.c
+ */
+void pirq_assign_irqs(const unsigned char pIntAtoD[4])
+{
+ return;
+}
+
Index: src/mainboard/nokia/ip530/mainboard.c
===================================================================
--- src/mainboard/nokia/ip530/mainboard.c (revision 5600)
+++ src/mainboard/nokia/ip530/mainboard.c (working copy)
@@ -20,7 +20,44 @@
#include <device/device.h>
#include "chip.h"
+#include <device/pci_def.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <console/console.h>
+#define OUTB outb
+#define INB inb
+/*
+* Taken from flashrom project
+* Generic Super I/O helper functions
+*/
+static uint8_t sio_read(uint16_t port, uint8_t reg)
+{
+ OUTB( reg, port );
+ return ( INB( port + 1 ) );
+}
+
+static void sio_write(uint16_t port, uint8_t reg, uint8_t data)
+{
+ OUTB( reg, port );
+ OUTB( data, port + 1 );
+ return;
+}
+
+static void nokia_ip530_board_enable( device_t dev )
+{
+ print_debug( "Setting up IP530-Super I/O devices\n");
+ sio_write( 0x20, 0x03, 0x80 );
+ printk( BIOS_DEBUG, "--Register 0x03 = %X := 0x80\n", sio_read( 0x20, 0x03 ) );
+ sio_write( 0x20, 0x22, 0x30 );
+ printk( BIOS_DEBUG, "--Register 0x22 = %X := 0x30\n", sio_read( 0x20, 0x22 ) );
+ sio_write( 0x20, 0x24, 0x84 );
+ printk( BIOS_DEBUG, "--Register 0x24 = %X := 0x84\n", sio_read( 0x20, 0x24 ) );
+ return;
+}
+
struct chip_operations mainboard_ops = {
- CHIP_NAME("Nokia IP530 Mainboard")
+ CHIP_NAME("NOKIA IP530 Mainboard")
+ .enable_dev = nokia_ip530_board_enable,
};
--
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