On Thu, Jun 10, 2010 at 03:30:09PM -0400, Arne Georg Gleditsch wrote: > Joe Korty <[email protected]> writes: > >> This sounds kinda familiar. Can you check if it is related to > >> http://article.gmane.org/gmane.linux.bios/57707 -- do the patches there > >> help any? > > > > Doesn't look like it. We are getting hosed (consuming an hour's worth of > > time) > > between the printk of 'Clearing memory...' and the printk of 'Done.' The > > only > > thing between those two printk's is a memset. > > I believe there's a patch to memset there too, unless I've pasted the > wrong URL? I saw what appeared to be dramatic performance issues, > presumably related to instruction cache misses/refetches in the memset > code. (The impact is likely related to how the alignment turns out as > well as the latency over the SB towards ROM.) > > I'm not sure a northbridge timeout on write to coherent memory would be > benign enough to let you continue going gracefully... Either way, it'd > be interesting to know if modifying the code itself helps any.
Hi Arne, First first applied only the memset change then I applied the whole patch. The memset-only change did indeed speed up the memset. It is now instantaeous. The speedup seems too great to me, it implies that I've no-oped memset somehow. Then I applied the whole patch. I had to change the "#if CONFIG_ARCH_X86" to "#if 1" as CONFIG_ARCH_X86 doesn't seem to be set. With that single change to your patch I see a speed-up to 'no delays, anywhere'; but now the execution patch is quite a bit different, we are in a warm reset infinite loop. Anyways your patch made a difference ....... Thanks, Joe -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
