Andriy Gapon wrote: > > Maybe you already know this, but I would not expect the superio to be > > involved very much in the dualbios mechanism - at most an IO pin > > would be used for the handshake with the patented timer. > > Still I would like to get the spec.
Yes, fair enough. :) > It may also depend on a particular motherboard, chip, etc. Perhaps > the "patented timer" is implemented in Super I/O. I doubt this since Gigabyte owns the patent for the dual bios invention, and ITE is unrelated to Gigabyte. The dual bios invention might *use* a timer within the superio though - that's possible. > At least, we see that some undocumented Super I/O register(s) are > used to switch between the flash chips and some other related > things. IO pins and timer on the superio could certainly be used. //Peter -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
