>> From your mainboard's Kconfig:
>>
>> +config DIMM_SUPPORT
>> + hex
>> + default 0x0004
>> + depends on CPU_AMD_SOCKET_AM3
>>
>> This really worries me. You shouldn't need to change the type of memory
>> on
>> the Socket. I looked at your board online, and they suggest that your
>> board
>> supports socket AM2, AM2+, and AM3. That seems like it breaks our model.
>> I
>> thought AM2 was DDR2 and AM3 was DDR3.
>
> Sorry to break your design, but that was what I had to do to get the RAM
> working.
I wasn't offended. I just want to improve the design if it's broken.
> I can confirm that I am using DDR2 memory and the CPU is this:
>
> http://products.amd.com/en-na/DesktopCPUDetail.aspx?id=615
Thanks.
>> In general, the fewer changes the better!
>
> I agree. The patches could be smaller and neater.
>
> However, I cannot hold on to this board for arbitrarily long, since I should
> put it to production use now that Coreboot is working. I will see what I
> can do to reduce these patches further, if I just find a suitable slot of
> time.
I appreciate the work that you've done. I've attached patches that
I've reduced a little more. Would you test/review them? If they
work, I'll commit them.
Signed-off-by: Myles Watson <[email protected]>
Thanks,
Myles
Index: svn/src/mainboard/asus/m4a785-m/Kconfig
===================================================================
--- svn.orig/src/mainboard/asus/m4a785-m/Kconfig
+++ svn/src/mainboard/asus/m4a785-m/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_AMD_TILAPIA_FAM10
+if BOARD_ASUS_M4A785M
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@@ -7,7 +7,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_AMD_AMDFAM10
select SOUTHBRIDGE_AMD_RS780
select SOUTHBRIDGE_AMD_SB700
- select SUPERIO_ITE_IT8718F
+ select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
+ select SUPERIO_ITE_IT8712F
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
@@ -26,9 +27,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select TINY_BOOTBLOCK
select GFXUMA
+config DIMM_SUPPORT
+ hex
+ default 0x0004
+
config MAINBOARD_DIR
string
- default amd/tilapia_fam10
+ default asus/m4a785-m
config APIC_ID_OFFSET
hex
@@ -36,7 +41,7 @@ config APIC_ID_OFFSET
config MAINBOARD_PART_NUMBER
string
- default "Tilapia (Fam10)"
+ default "M4A785-M"
config HW_MEM_HOLE_SIZEK
hex
@@ -72,7 +77,7 @@ config HT_CHAIN_UNITID_BASE
config IRQ_SLOT_COUNT
int
- default 11
+ default 19
config AMD_UCODE_PATCH_FILE
string
@@ -92,11 +97,11 @@ config ACPI_SSDTX_NUM
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
- default 0x3060
+ default 0x83a2
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
- default 0x1022
+ default 0x1043
config RAMBASE
hex
@@ -106,4 +111,4 @@ config COMPRESS
hex
default 0
-endif # BOARD_AMD_TILAPIA_FAM10
+endif
Index: svn/src/mainboard/asus/m4a785-m/devicetree.cb
===================================================================
--- svn.orig/src/mainboard/asus/m4a785-m/devicetree.cb
+++ svn/src/mainboard/asus/m4a785-m/devicetree.cb
@@ -1,7 +1,6 @@
-# sample config for amd/tilapia_fam10
chip northbridge/amd/amdfam10/root_complex
device lapic_cluster 0 on
- chip cpu/amd/socket_AM3 #L1 and DDR3
+ chip cpu/amd/socket_AM3 #L1 and DDR2
device lapic 0 on end
end
end
@@ -11,15 +10,15 @@ chip northbridge/amd/amdfam10/root_compl
chip southbridge/amd/rs780
device pci 0.0 on end # HT 0x9600
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
- device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
- device pci 3.0 on end # PCIE P2P bridge 0x960b
- device pci 4.0 on end # PCIE P2P bridge 0x9604
+ device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
+ device pci 3.0 off end # PCIE P2P bridge 0x960b
+ device pci 4.0 off end # PCIE P2P bridge 0x9604
device pci 5.0 off end # PCIE P2P bridge 0x9605
device pci 6.0 off end # PCIE P2P bridge 0x9606
device pci 7.0 off end # PCIE P2P bridge 0x9607
device pci 8.0 off end # NB/SB Link P2P bridge
- device pci 9.0 on end #
- device pci a.0 on end #
+ device pci 9.0 off end #
+ device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet
register "gppsb_configuration" = "1" # Configuration B
register "gpp_configuration" = "3" # Configuration D default
register "port_enable" = "0x6fc"
@@ -57,12 +56,8 @@ chip northbridge/amd/amdfam10/root_compl
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
- chip superio/ite/it8718f
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
+ chip superio/ite/it8712f
+ device pnp 2e.0 off end # Floppy
device pnp 2e.1 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
@@ -75,7 +70,7 @@ chip northbridge/amd/amdfam10/root_compl
io 0x60 = 0x378
irq 0x70 = 7
end
- device pnp 2e.4 off end # EC
+ device pnp 2e.4 off end # Environment Controller
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
@@ -87,16 +82,13 @@ chip northbridge/amd/amdfam10/root_compl
device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
end
device pnp 2e.8 off # MIDI
- io 0x60 = 0x300
- irq 0x70 = 9
end
device pnp 2e.9 off # GAME
- io 0x60 = 0x220
end
device pnp 2e.a off end # CIR
- end #superio/ite/it8718f
+ end #superio
end #LPC
- device pci 14.4 on end # PCI 0x4384
+ device pci 14.4 on end # PCI to PCI Bridge [1002:4384]
device pci 14.5 on end # USB 2
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/sb700
@@ -108,35 +100,6 @@ chip northbridge/amd/amdfam10/root_compl
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
-# device pci 00.5 on end
- end
+ end # chip northbridge
end #pci_domain
- #for node 32 to node 63
-# device pci_domain 0 on
-# chip northbridge/amd/amdfam10
-# device pci 00.0 on end# northbridge
-# device pci 00.0 on end
-# device pci 00.0 on end
-# device pci 00.0 on end
-# device pci 00.1 on end
-# device pci 00.2 on end
-# device pci 00.3 on end
-# device pci 00.4 on end
-# device pci 00.5 on end
-# end
-# end #pci_domain
-
-# chip drivers/generic/debug
-# device pnp 0.0 off end # chip name
-# device pnp 0.1 on end # pci_regs_all
-# device pnp 0.2 off end # mem
-# device pnp 0.3 off end # cpuid
-# device pnp 0.4 off end # smbus_regs_all
-# device pnp 0.5 off end # dual core msr
-# device pnp 0.6 off end # cache size
-# device pnp 0.7 off end # tsc
-# device pnp 0.8 off end # hard reset
-# device pnp 0.9 off end # mcp55
-# device pnp 0.a on end # GH ext table
-# end
-end
+end # northbridge/amd/amdfam10/root_complex
Index: svn/src/mainboard/asus/m4a785-m/romstage.c
===================================================================
--- svn.orig/src/mainboard/asus/m4a785-m/romstage.c
+++ svn/src/mainboard/asus/m4a785-m/romstage.c
@@ -59,7 +59,7 @@
static int smbus_read_byte(u32 device, u32 address);
-#include "superio/ite/it8718f/it8718f_early_serial.c"
+#include "superio/ite/it8712f/it8712f_early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -136,7 +136,8 @@ void cache_as_ram_main(unsigned long bis
enable_rs780_dev8();
sb700_lpc_init();
- it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
+ it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+ it8712f_kill_watchdog(); /* disable watchdog, so it does not reset while still booting */
uart_init();
console_init();
printk(BIOS_DEBUG, "\n");
Index: svn/src/mainboard/asus/m4a785-m/irq_tables.c
===================================================================
--- svn.orig/src/mainboard/asus/m4a785-m/irq_tables.c
+++ svn/src/mainboard/asus/m4a785-m/irq_tables.c
@@ -1,11 +1,12 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 200x TODO <t...@todo>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -17,97 +18,48 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
#include <arch/pirq_routing.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-
-
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
- u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
- u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
- u8 slot, u8 rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-extern u8 bus_isa;
-extern u8 bus_rs780[8];
-extern u8 bus_sb700[2];
-extern unsigned long sbdn_sb700;
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * 19, /* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x14 << 3) | 0x3, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x1002, /* Vendor */
+ 0x439d, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x8, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x01, (0x05 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x02 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x03 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x04 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x05 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x06 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x07 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x09 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x0a << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x02, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0xa, 0x0},
+ {0x00, (0x0b << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x0c << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x14 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x12 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x13 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x00, (0x11 << 3) | 0x0, {{0x0c, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x0a, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
+ {0x03, (0x05 << 3) | 0x0, {{0x0a, 0xdc90}, {0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}}, 0xc, 0x0},
+ {0x03, (0x06 << 3) | 0x0, {{0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}, {0x0a, 0xdc90}}, 0xd, 0x0},
+ }
+};
unsigned long write_pirq_routing_table(unsigned long addr)
{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- u32 slot_num;
- u8 *v;
-
- u8 sum = 0;
- int i;
-
- get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be betweeen 0xf0000 & 0x100000 */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (u8 *) (addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = bus_sb700[0];
- pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1002;
- pirq->rtr_device = 0x4384;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* pci bridge */
- write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4,
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
- return (unsigned long)pirq_info;
+ return copy_pirq_routing_table(addr);
}
Index: svn/src/mainboard/asus/m4a785-m/mainboard.c
===================================================================
--- svn.orig/src/mainboard/asus/m4a785-m/mainboard.c
+++ svn/src/mainboard/asus/m4a785-m/mainboard.c
@@ -46,6 +46,9 @@ extern int do_smbus_write_byte(u32 smbus
uint64_t uma_memory_base, uma_memory_size;
+#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+
void set_pcie_dereset(void);
void set_pcie_reset(void);
u8 is_dev3_present(void);
@@ -132,6 +135,8 @@ static void get_ide_dma66(void)
/*
* justify the dev3 is exist or not
+ * NOTE: This just copied from AMD Tilapia code.
+ * It is completly unknown it it will work at all for Asus M4A785-A
*/
u8 is_dev3_present(void)
{
@@ -158,62 +163,6 @@ u8 is_dev3_present(void)
}
}
-
-/*
- * set gpio40 gfx
- */
-static void set_gpio40_gfx(void)
-{
- u8 byte;
- u32 dword;
- device_t sm_dev;
- /* disable the GPIO40 as CLKREQ2# function */
- byte = pm_ioread(0xd3);
- byte &= ~(1 << 7);
- pm_iowrite(0xd3, byte);
-
- /* disable the GPIO40 as CLKREQ3# function */
- byte = pm_ioread(0xd4);
- byte &= ~(1 << 0);
- pm_iowrite(0xd4, byte);
-
- /* enable pull up for GPIO68 */
- byte = pm2_ioread(0xf1);
- byte &= ~(1 << 4);
- pm2_iowrite(0xf1, byte);
-
- /* access the smbus extended register */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
- /*if the dev3 is present, set the gfx to 2x8 lanes*/
- /*otherwise set the gfx to 1x16 lanes*/
- if(is_dev3_present()){
-
- printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n");
- /* when the gpio40 is configured as GPIO, this will enable the output */
- pci_write_config32(sm_dev, 0xf8, 0x4);
- dword = pci_read_config32(sm_dev, 0xfc);
- dword &= ~(1 << 10);
-
- /* When the gpio40 is configured as GPIO, this will represent the output value*/
- /* 1 :enable two x8 , 0 : master slot enable only */
- dword |= (1 << 26);
- pci_write_config32(sm_dev, 0xfc, dword);
-
- }else{
- printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
- /* when the gpio40 is configured as GPIO, this will enable the output */
- pci_write_config32(sm_dev, 0xf8, 0x4);
- dword = pci_read_config32(sm_dev, 0xfc);
- dword &= ~(1 << 10);
-
- /* When the gpio40 is configured as GPIO, this will represent the output value*/
- /* 1 :enable two x8 , 0 : master slot enable only */
- dword &= ~(1 << 26);
- pci_write_config32(sm_dev, 0xfc, dword);
- }
-}
-
/*
* set thermal config
*/
@@ -279,12 +228,12 @@ static void set_thermal_config(void)
}
/*************************************************
-* enable the dedicated function in tilapia board.
+* enable the dedicated function in m4a785m board.
* This function called early than rs780_enable.
*************************************************/
-static void tilapia_enable(device_t dev)
+static void m4a785m_enable(device_t dev)
{
- printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev);
+ printk(BIOS_INFO, "Mainboard M4A785M Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
msr_t msr, msr2;
@@ -325,10 +274,13 @@ static void tilapia_enable(device_t dev)
uma_memory_base = 0x38000000; /* 1GB system memory supposed */
#endif
+ // set location of Coreboot high_tables just below UMA
+ high_tables_size = HIGH_TABLES_SIZE * 1024; // convert KB to B
+ high_tables_base = uma_memory_base - high_tables_size;
+
set_pcie_dereset();
/* get_ide_dma66(); */
set_thermal_config();
- set_gpio40_gfx();
}
int add_mainboard_resources(struct lb_memory *mem)
@@ -346,6 +298,6 @@ int add_mainboard_resources(struct lb_me
}
struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD TILAPIA Mainboard")
- .enable_dev = tilapia_enable,
+ CHIP_NAME("AMD M4A785M Mainboard")
+ .enable_dev = m4a785m_enable,
};
Index: svn/src/mainboard/asus/Kconfig
===================================================================
--- svn.orig/src/mainboard/asus/Kconfig
+++ svn/src/mainboard/asus/Kconfig
@@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE
bool "A8V-E SE"
config BOARD_ASUS_M2V_MX_SE
bool "M2V-MX SE"
+config BOARD_ASUS_M4A785M
+ bool "M4A785-M"
config BOARD_ASUS_MEW_AM
bool "MEW-AM"
config BOARD_ASUS_MEW_VM
@@ -49,6 +51,7 @@ endchoice
source "src/mainboard/asus/a8n_e/Kconfig"
source "src/mainboard/asus/a8v-e_se/Kconfig"
source "src/mainboard/asus/m2v-mx_se/Kconfig"
+source "src/mainboard/asus/m4a785-m/Kconfig"
source "src/mainboard/asus/mew-am/Kconfig"
source "src/mainboard/asus/mew-vm/Kconfig"
source "src/mainboard/asus/p2b/Kconfig"
Index: svn/src/devices/pci_device.c
===================================================================
--- svn.orig/src/devices/pci_device.c
+++ svn/src/devices/pci_device.c
@@ -1019,6 +1019,14 @@ unsigned int pci_scan_bus(struct bus *bu
printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
#endif
+ // Maximum sane devfn is 0xFF
+ if (max_devfn > 0xff) {
+ printk(BIOS_ERR, "PCI: pci_scan_bus limits devfn %x - devfn %x\n",
+ min_devfn, max_devfn );
+ printk(BIOS_ERR, "PCI: pci_scan_bus upper limit too big. Using 0xff.\n");
+ max_devfn=0xff;
+ }
+
old_devices = bus->children;
bus->children = NULL;
Index: svn/src/southbridge/amd/sb700/sb700_lpc.c
===================================================================
--- svn.orig/src/southbridge/amd/sb700/sb700_lpc.c
+++ svn/src/southbridge/amd/sb700/sb700_lpc.c
@@ -42,7 +42,11 @@ static void lpc_init(device_t dev)
pci_write_config32(sm_dev, 0x64, dword);
/* Initialize isa dma */
+#if CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
+ printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n");
+#else
isa_dma_init();
+#endif
/* Enable DMA transaction on the LPC bus */
byte = pci_read_config8(dev, 0x40);
Index: svn/src/southbridge/amd/sb700/Kconfig
===================================================================
--- svn.orig/src/southbridge/amd/sb700/Kconfig
+++ svn/src/southbridge/amd/sb700/Kconfig
@@ -20,3 +20,9 @@
config SOUTHBRIDGE_AMD_SB700
bool
select IOAPIC
+
+config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
+ bool
+ default n
+ depends on SOUTHBRIDGE_AMD_SB700
+
Index: svn/src/arch/i386/boot/multiboot.c
===================================================================
--- svn.orig/src/arch/i386/boot/multiboot.c
+++ svn/src/arch/i386/boot/multiboot.c
@@ -22,62 +22,16 @@
#include <string.h>
#include <device/resource.h>
#include <console/console.h>
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
-static struct multiboot_mmap_entry *mb_mem;
struct multiboot_info *mbi = NULL;
-static struct {
- u64 addr;
- u64 len;
-} reserved_mem[2];
-
-static void build_mb_mem_range_nooverlap(u64 addr, u64 len)
-{
- int i;
- for (i = 0; i < sizeof(reserved_mem) / sizeof(reserved_mem[0]); i++) {
- /* free region fully contained in reserved region, abort */
- if (addr >= reserved_mem[i].addr && addr + len <= reserved_mem[i].addr + reserved_mem[i].len)
- return;
- /* reserved region splits free region */
- if (addr < reserved_mem[i].addr && addr + len > reserved_mem[i].addr + reserved_mem[i].len) {
- build_mb_mem_range_nooverlap(addr, reserved_mem[i].addr - addr);
- build_mb_mem_range_nooverlap(reserved_mem[i].addr + reserved_mem[i].len, (addr + len) - (reserved_mem[i].addr + reserved_mem[i].len));
- return;
- }
- /* left overlap */
- if (addr < reserved_mem[i].addr + reserved_mem[i].len && addr + len > reserved_mem[i].addr + reserved_mem[i].len) {
- len += addr;
- addr = reserved_mem[i].addr + reserved_mem[i].len;
- len -= addr;
- /* len += addr - old_addr */
- continue;
- }
- /* right overlap */
- if (addr < reserved_mem[i].addr && addr + len > reserved_mem[i].addr) {
- len = reserved_mem[i].addr - addr;
- continue;
- }
- /* none of the above, just add it */
- }
-
- mb_mem->addr = addr;
- mb_mem->len = len;
- mb_mem->type = 1;
- mb_mem->size = sizeof(*mb_mem) - sizeof(mb_mem->size);
- mb_mem++;
-}
-
-static void build_mb_mem_range(void *gp, struct device *dev, struct resource *res)
-{
- build_mb_mem_range_nooverlap(res->base, res->size);
-}
-
-#define ROUND(_r,_a) (((_r) + (((_a) - 1))) & ~((_a) - 1))
-
-unsigned long write_multiboot_info(
- unsigned long low_table_start, unsigned long low_table_end,
- unsigned long rom_table_start, unsigned long rom_table_end)
+unsigned long write_multiboot_info(unsigned long rom_table_end)
{
+ static struct multiboot_mmap_entry *mb_mem;
+ struct lb_memory* coreboot_table;
+ int entries;
int i;
mbi = (struct multiboot_info *)rom_table_end;
@@ -88,26 +42,31 @@ unsigned long write_multiboot_info(
mbi->mmap_addr = (u32) rom_table_end;
mb_mem = (struct multiboot_mmap_entry *)rom_table_end;
- /* FIXME This code is broken, it does not know about high memory
- * tables, nor does it reserve the coreboot table area.
- */
- /* reserved regions */
- reserved_mem[0].addr = low_table_start;
- reserved_mem[0].len = ROUND(low_table_end - low_table_start, 4096);
- reserved_mem[1].addr = rom_table_start;
- reserved_mem[1].len = ROUND(rom_table_end - rom_table_start, 4096);
-
- for (i = 0; i < sizeof(reserved_mem) / sizeof(reserved_mem[0]); i++) {
- mb_mem->addr = reserved_mem[i].addr;
- mb_mem->len = reserved_mem[i].len;
- mb_mem->type = 2;
- mb_mem->size = sizeof(*mb_mem) - sizeof(mb_mem->size);
- mb_mem++;
+ /* copy regions from coreboot tables */
+ coreboot_table = get_lb_mem();
+ entries = (coreboot_table->size - sizeof(*coreboot_table))/sizeof(coreboot_table->map[0]);
+
+ if (coreboot_table == NULL || entries < 1) {
+ printk(BIOS_INFO, "%s: Cannot find coreboot table.\n", __func__);
+ return (unsigned long) mb_mem;
}
- /* free regions */
- search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE,
- IORESOURCE_MEM | IORESOURCE_CACHEABLE, build_mb_mem_range, NULL);
+ for (i = 0; i < entries; i++) {
+ uint64_t entry_start = unpack_lb64(coreboot_table->map[i].start);
+ uint64_t entry_size = unpack_lb64(coreboot_table->map[i].size);
+ mb_mem->addr = entry_start;
+ mb_mem->len = entry_size;
+ switch (coreboot_table->map[i].type) {
+ case LB_MEM_RAM:
+ mb_mem->type = MULTIBOOT_MEMORY_AVAILABLE;
+ break;
+ default: // anything other than usable RAM
+ mb_mem->type = MULTIBOOT_MEMORY_RESERVED;
+ break;
+ }
+ mb_mem->size = sizeof(*mb_mem) - sizeof(mb_mem->size);
+ mb_mem++;
+ }
mbi->mmap_length = ((u32) mb_mem) - mbi->mmap_addr;
mbi->flags |= MB_INFO_MEM_MAP;
Index: svn/src/arch/i386/boot/tables.c
===================================================================
--- svn.orig/src/arch/i386/boot/tables.c
+++ svn/src/arch/i386/boot/tables.c
@@ -179,14 +179,6 @@ struct lb_memory *write_tables(void)
#endif
-#if CONFIG_MULTIBOOT
- post_code(0x9d);
-
- /* The Multiboot information structure */
- rom_table_end = write_multiboot_info(
- low_table_start, low_table_end,
- rom_table_start, rom_table_end);
-#endif
#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
post_code(0x9d);
@@ -210,8 +202,9 @@ struct lb_memory *write_tables(void)
new_high_table_pointer - high_table_pointer);
} else {
/* The coreboot table must be in 0-4K or 960K-1M */
- write_coreboot_table(low_table_start, low_table_end,
- rom_table_start, rom_table_end);
+ rom_table_end = write_coreboot_table(
+ low_table_start, low_table_end,
+ rom_table_start, rom_table_end);
}
post_code(0x9e);
@@ -224,6 +217,13 @@ struct lb_memory *write_tables(void)
cbmem_add(CBMEM_ID_RESUME, 1024 * (1024-64));
#endif
+#if CONFIG_MULTIBOOT
+ post_code(0x9d);
+
+ /* The Multiboot information structure */
+ write_multiboot_info(rom_table_end);
+#endif
+
// Remove before sending upstream
cbmem_list();
Index: svn/src/include/cpu/x86/multiboot.h
===================================================================
--- svn.orig/src/include/cpu/x86/multiboot.h
+++ svn/src/include/cpu/x86/multiboot.h
@@ -167,6 +167,9 @@ struct multiboot_info {
uint16_t vbe_interface_len;
};
+#define MULTIBOOT_MEMORY_AVAILABLE 1
+#define MULTIBOOT_MEMORY_RESERVED 2
+
struct multiboot_mmap_entry {
uint32_t size;
uint64_t addr;
@@ -176,6 +179,6 @@ struct multiboot_mmap_entry {
extern struct multiboot_info *mbi;
-unsigned long write_multiboot_info(unsigned long, unsigned long, unsigned long, unsigned long);
+unsigned long write_multiboot_info(unsigned long rom_table_end);
#endif
--
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