Author: zbao Date: Tue Sep 28 06:43:16 2010 New Revision: 5874 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5874
Log: Trivial. re-Indent the code. Signed-off-by: Zheng Bao <[email protected]> Acked-by: Zheng Bao <[email protected]> Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.c Mon Sep 27 23:28:21 2010 (r5873) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.c Tue Sep 28 06:43:16 2010 (r5874) @@ -776,7 +776,7 @@ if (val == dword) /* current nodeID = requested nodeID ? */ ret = 1; finish: - ; + ; } return ret; @@ -1040,33 +1040,33 @@ if (byte & 0xF0) { val++; /* round up in case fractional extention is non-zero.*/ } - } - if (Trc < val) - Trc = val; - - /* dev density=rank size/#devs per rank */ - byte = mctRead_SPD(smbaddr, SPD_BANKSZ); - - val = ((byte >> 5) | (byte << 3)) & 0xFF; - val <<= 2; - - byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density=2^(rows+columns+banks) */ - if (byte == 4) { - val >>= 4; - } else if (byte == 8) { - val >>= 3; - } else if (byte == 16) { - val >>= 2; - } + } + if (Trc < val) + Trc = val; - byte = bsr(val); + /* dev density=rank size/#devs per rank */ + byte = mctRead_SPD(smbaddr, SPD_BANKSZ); - if (Trfc[LDIMM] < byte) - Trfc[LDIMM] = byte; + val = ((byte >> 5) | (byte << 3)) & 0xFF; + val <<= 2; - byte = mctRead_SPD(smbaddr, SPD_TRAS); - if (Tras < byte) - Tras = byte; + byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density=2^(rows+columns+banks) */ + if (byte == 4) { + val >>= 4; + } else if (byte == 8) { + val >>= 3; + } else if (byte == 16) { + val >>= 2; + } + + byte = bsr(val); + + if (Trfc[LDIMM] < byte) + Trfc[LDIMM] = byte; + + byte = mctRead_SPD(smbaddr, SPD_TRAS); + if (Tras < byte) + Tras = byte; } /* Dimm Present */ } @@ -1129,7 +1129,7 @@ } pDCTstat->Trp = val; - /*Trrd*/ + /*Trrd*/ dword = Trrd * 10; pDCTstat->DIMMTrrd = dword; val = dword / Tk40; @@ -2183,8 +2183,8 @@ pDCTstat->DimmECCPresent |= 1 << i; } if (byte & JED_ADRCPAR) { - /* DIMM is ECC capable */ - pDCTstat->DimmPARPresent |= 1 << i; + /* DIMM is ECC capable */ + pDCTstat->DimmPARPresent |= 1 << i; } /* Check if x4 device */ devwidth = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; @@ -2455,8 +2455,8 @@ if (byte != bytex) { pDCTstat->ErrStatus &= ~(1 << SB_DimmMismatchO); } else { - if ( mctGet_NVbits(NV_Unganged) ) - pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); + if ( mctGet_NVbits(NV_Unganged) ) + pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); if (!(pDCTstat->ErrStatus & (1 << SB_DimmMismatchO))) { pDCTstat->GangedMode = 1; @@ -2872,7 +2872,7 @@ dword = bsr(pDCTstat->DIMMValid); if (dword != val && dword != 0) { /*the largest WrDatGrossDlyByte of any DIMM minus the - WrDatGrossDlyByte of any other DIMM is equal to CGDD */ + WrDatGrossDlyByte of any other DIMM is equal to CGDD */ val = Get_WrDatGross_Diff(pDCTstat, dct, dev, index_reg); } if (val == 0) @@ -3128,7 +3128,7 @@ Largest = byte; } } - index += 3; + index += 3; } /* while ++i */ word = Smallest; @@ -3265,7 +3265,7 @@ dev = pDCTstat->dev_map; /* Copy dram map from F1x40/44,F1x48/4c, - to F1x120/124(Node0),F1x120/124(Node1),...*/ + to F1x120/124(Node0),F1x120/124(Node1),...*/ for (Node=0; Node < MAX_NODES_SUPPORTED; Node++) { pDCTstat = pDCTstatA + Node; devx = pDCTstat->dev_map; @@ -3738,7 +3738,7 @@ Set_NB32_index_wait(dev, index_reg, index, val | (1 << DisAutoComp)); //FIXME: check for Bx Cx CPU - // if Ax mct_SetDramConfigHi_Samp_D + // if Ax mct_SetDramConfigHi_Samp_D /* errata#177 */ index = 0x4D014F00; /* F2x[1, 0]9C_x[D0FFFFF:D000000] DRAM Phy Debug Registers */ Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Mon Sep 27 23:28:21 2010 (r5873) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Tue Sep 28 06:43:16 2010 (r5874) @@ -2814,7 +2814,7 @@ Largest = byte; } } - index += 3; + index += 3; } /* while ++i */ word = Smallest; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
