-----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Rudolf Marek Sent: Tuesday, November 02, 2010 05:03 PM To: [email protected] Subject: Re: [coreboot] [PATCH] Fix AMD HD 3200 uma graphics problems in Win7
]Hi Scott! ] ]Thank you very much working on this! I wanted to try out but Igot hang in early ]init (car stage). Most likely because of this: ] ]> =================================================================== ]> --- src/southbridge/amd/rs780/rs780_early_setup.c (revision 6011) ]> +++ src/southbridge/amd/rs780/rs780_early_setup.c (working copy) ]> @@ -485,7 +485,7 @@ ]> ]> /*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR, ]> * force this BAR as mem type in rs780_gfx.c */ ]> - set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03); ]> + set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x06); ]> } ]> ]> static void rs780_por_mc_index_init(device_t nb_dev) ]> Index: src/southbridge/amd/rs780/rs780_gfx.c ] ]Can you please tell what it does? Hello Rudolf, Thanks for taking time to test this patch. I assume you tested with a family 0Fh processor. The mistake I made was testing only with family 10h, which is how this problem slipped through. Here are the bit definitions: F2_MULTI_FUNC_ENABLE 8 GFX_DEBUG_BAR_ENABLE 9 GFX_DEBUG_DECODE_ENABLE 10 The original code was incorrect to set bit 8 because the reference BIOS does not set it. But that may be insignificant. I believe the real problem is this. The following sequence is needed needed to reliably enable the gfx debug bar (bar 6 of bus 1, device 5, function 0): 1) Set bit 9 so that the bar is writable and can be programmed. 2) Allow the resource allocation code assign a range to the debug bar. 3) Set bit 10 to let the debug start decoding its range. The debug bar is a back door into the pci config space of the RS780. If it is not setup and working, the ATI graphics driver will not work. I will re-sumbit the patch with this change. I still have to port some ACPI changes from mahogany_fam10 to mahogany before I can test Win7 the family 0Fh processor. Thanks, Scott ]Thanks, ]Rudolf -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot

