Hi,
I moved the SET_FIDVID family of configuration options to Kconfig,
adapting its use (CONFIG_ prefix), and tried to minimize the board
specific settings.
They get some defaults in src/cpu/amd/model_*xx/Kconfig, which are
derived from the various #ifndef ... #define ... #endif blocks I removed
in the cpu specific code.
All "#define SET_FIDVID 0" in romstage.c files weren't necessary due to
these defaults, as well as all "#define SET_FIDVID 1" in Fam10 boards,
so these were stripped.
Some "select SET_FIDVID" could probably still be removed.
SET_FIDVID_CORE_RANGE was always 0, so I just chose that in the CPU
config, instead of per-board.
SET_FIDVID_CORE0_ONLY was always 1, so again, I moved this to the CPU.
Any change in SET_FIDVID* configuration values as a result of this patch
is a bug in this patch.
Regards,
Patrick
Move SET_FIDVID family of configuration options to Kconfig.
Reduce their per-board use and rely on per-cpu values instead.
Signed-off-by: Patrick Georgi <[email protected]>
Index: src/cpu/amd/model_fxx/Kconfig
===================================================================
--- src/cpu/amd/model_fxx/Kconfig (Revision 6029)
+++ src/cpu/amd/model_fxx/Kconfig (Arbeitskopie)
@@ -4,7 +4,31 @@
select SSE
select SSE2
+if CPU_AMD_MODEL_FXX
config UDELAY_IO
bool
default n
- depends on CPU_AMD_MODEL_FXX
+
+config SET_FIDVID
+ bool
+ default n
+ default y if K8_REV_F_SUPPORT
+
+if SET_FIDVID
+config SET_FIDVID_DEBUG
+ bool
+ default n
+
+config SET_FIDVID_CORE0_ONLY
+ bool
+ default y
+
+config SET_FIDVID_ONE_BY_ONE
+ bool
+ default y
+
+config SET_FIDVID_STORE_AP_APICID_AT_FIRST
+ bool
+ default y
+endif
+endif
Index: src/cpu/amd/model_fxx/fidvid.c
===================================================================
--- src/cpu/amd/model_fxx/fidvid.c (Revision 6029)
+++ src/cpu/amd/model_fxx/fidvid.c (Arbeitskopie)
@@ -1,11 +1,5 @@
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
-#define SET_FIDVID_DEBUG 0
-
-#define SET_FIDVID_ONE_BY_ONE 1
-
-#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
-
#ifndef SB_VFSMAF
#define SB_VFSMAF 1
#endif
@@ -14,21 +8,21 @@
static inline void print_debug_fv(const char *str, u32 val)
{
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
printk(BIOS_DEBUG, "%s%x\n", str, val);
#endif
}
static inline void print_debug_fv_8(const char *str, u8 val)
{
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
printk(BIOS_DEBUG, "%s%02x\n", str, val);
#endif
}
static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
{
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
#endif
}
@@ -70,7 +64,7 @@
}
}
-#if SET_FIDVID_ONE_BY_ONE == 0
+#if !CONFIG_SET_FIDVID_ONE_BY_ONE
static unsigned set_fidvid_without_init(unsigned fidvid)
{
msr_t msr;
@@ -276,7 +270,7 @@
ldtstop_sb();
#endif
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
if (showmessage) {
print_debug_fv_8("set_fidvid APICID = ", apicid);
print_debug_fv_64("fidvid ctrl msr ", msr.hi, msr.lo);
@@ -290,7 +284,7 @@
}
fid_cur = msr.lo & 0x3f;
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
if (showmessage) {
print_debug_fv_64("fidvid status msr ", msr.hi, msr.lo);
}
@@ -368,7 +362,7 @@
send |= ((msr.hi >> (48 - 32)) & 0x3f) << 16; /* max vid */
send |= (apicid << 24); /* ap apicid */
-#if SET_FIDVID_ONE_BY_ONE == 1
+#if CONFIG_SET_FIDVID_ONE_BY_ONE
vid_cur = msr.hi & 0x3f;
fid_cur = msr.lo & 0x3f;
@@ -399,7 +393,7 @@
}
if (loop > 0) {
-#if SET_FIDVID_ONE_BY_ONE == 1
+#if CONFIG_SET_FIDVID_ONE_BY_ONE
readback = set_fidvid(apicid, readback & 0xffff00, 1); // this
AP
#else
readback = set_fidvid_without_init(readback & 0xffff00);
// this AP
@@ -502,7 +496,7 @@
print_debug_fv("\treadback=", readback);
}
-#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
struct ap_apicid_st {
u32 num;
unsigned apicid[16]; /* 8 way dual core need 16 */
@@ -524,7 +518,7 @@
struct fidvid_st fv;
-#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
struct ap_apicid_st ap_apicidx;
unsigned i;
#endif
@@ -551,16 +545,16 @@
/* calculate the common max fid/vid that could be used for
* all APs and BSP */
-#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
ap_apicidx.num = 0;
- for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, store_ap_apicid,
&ap_apicidx);
+ for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, store_ap_apicid,
&ap_apicidx);
for (i = 0; i < ap_apicidx.num; i++) {
init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
}
#else
- for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1,
&fv);
+ for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY,
init_fidvid_bsp_stage1, &fv);
#endif
#if 0
@@ -587,7 +581,7 @@
#endif
-#if SET_FIDVID_ONE_BY_ONE == 1
+#if CONFIG_SET_FIDVID_ONE_BY_ONE
/* set BSP fid and vid */
print_debug_fv("bsp apicid=", bsp_apicid);
fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);
@@ -601,15 +595,15 @@
fv.common_fidvid &= 0xffff00;
/* set state 2 allow is in init_fidvid_bsp_stage2 */
-#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
for (i = 0; i < ap_apicidx.num; i++) {
init_fidvid_bsp_stage2(ap_apicidx.apicid[i], &fv);
}
#else
- for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2,
&fv);
+ for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY,
init_fidvid_bsp_stage2, &fv);
#endif
-#if SET_FIDVID_ONE_BY_ONE == 0
+#if !CONFIG_SET_FIDVID_ONE_BY_ONE
/* set BSP fid and vid */
print_debug_fv("bsp apicid=", bsp_apicid);
fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);
Index: src/cpu/amd/model_fxx/init_cpus.c
===================================================================
--- src/cpu/amd/model_fxx/init_cpus.c (Revision 6029)
+++ src/cpu/amd/model_fxx/init_cpus.c (Arbeitskopie)
@@ -2,22 +2,6 @@
#include "option_table.h"
#endif
-//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and
CONFIG_LIFT_BSP_APIC_ID
-#ifndef SET_FIDVID
-#if CONFIG_K8_REV_F_SUPPORT == 0
- #define SET_FIDVID 0
-#else
- // for rev F, need to set FID to max
- #define SET_FIDVID 1
-#endif
-
-#endif
-
-#ifndef SET_FIDVID_CORE0_ONLY
- /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't
need to do twice */
- #define SET_FIDVID_CORE0_ONLY 1
-#endif
-
typedef void (*process_ap_t) (u32 apicid, void *gp);
//core_range = 0 : all cores
@@ -135,7 +119,7 @@
#define LAPIC_MSG_REG 0x380
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
static void init_fidvid_ap(u32 bsp_apicid, u32 apicid);
#endif
@@ -291,8 +275,8 @@
u32 timeout = 1;
u32 loop = 100;
-#if SET_FIDVID == 1
-#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1)
+#if CONFIG_SET_FIDVID
+#if (CONFIG_LOGICAL_CPUS == 1) && CONFIG_SET_FIDVID_CORE0_ONLY
if (id.coreid == 0) // only need set fid for core0
#endif
init_fidvid_ap(bsp_apicid, apicid);
Index: src/cpu/amd/model_10xxx/Kconfig
===================================================================
--- src/cpu/amd/model_10xxx/Kconfig (Revision 6029)
+++ src/cpu/amd/model_10xxx/Kconfig (Arbeitskopie)
@@ -4,27 +4,50 @@
select SSE
select SSE2
+if CPU_AMD_MODEL_10XXX
config CPU_ADDR_BITS
int
default 48
- depends on CPU_AMD_MODEL_10XXX
config DCACHE_RAM_BASE
hex
default 0xc4000
- depends on CPU_AMD_MODEL_10XXX
config DCACHE_RAM_SIZE
hex
default 0x0c000
- depends on CPU_AMD_MODEL_10XXX
config DCACHE_RAM_GLOBAL_VAR_SIZE
hex
default 0x04000
- depends on CPU_AMD_MODEL_10XXX
config UDELAY_IO
bool
default n
- depends on CPU_AMD_MODEL_10XXX
+
+config SET_FIDVID
+ bool
+ default y
+
+if SET_FIDVID
+config SET_FIDVID_DEBUG
+ bool
+ default y
+
+config SET_FIDVID_STORE_AP_APICID_AT_FIRST
+ bool
+ default y
+
+config SET_FIDVID_CORE0_ONLY
+ bool
+ default n
+
+# 0: all cores
+# 1: core 0 only
+# 2: all but core 0
+config SET_FIDVID_CORE_RANGE
+ int
+ default 0
+
+endif
+endif
Index: src/cpu/amd/model_10xxx/fidvid.c
===================================================================
--- src/cpu/amd/model_10xxx/fidvid.c (Revision 6029)
+++ src/cpu/amd/model_10xxx/fidvid.c (Arbeitskopie)
@@ -17,31 +17,26 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
#include <northbridge/amd/amdht/AsPsDefs.h>
-#define SET_FIDVID_DEBUG 1
-
-// if we are tight of CAR stack, disable it
-#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
-
static inline void print_debug_fv(const char *str, u32 val)
{
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
printk(BIOS_DEBUG, "%s%x\n", str, val);
#endif
}
static inline void print_debug_fv_8(const char *str, u8 val)
{
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
printk(BIOS_DEBUG, "%s%02x\n", str, val);
#endif
}
static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
{
-#if SET_FIDVID_DEBUG == 1
+#if CONFIG_SET_FIDVID_DEBUG
printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
#endif
}
@@ -729,7 +724,7 @@
}
-#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
struct ap_apicid_st {
u32 num;
// it could use 256 bytes for 64 node quad core system
@@ -748,7 +743,7 @@
static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
{
-#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
+#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
struct ap_apicid_st ap_apicidx;
u32 i;
#endif
@@ -806,20 +801,20 @@
fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8);
print_debug_fv("BSP fid = ", fv.common_fid);
-#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && SET_FIDVID_CORE0_ONLY == 0
+#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST && !CONFIG_SET_FIDVID_CORE0_ONLY
/* For all APs (We know the APIC ID of all APs even when the APIC ID
is lifted) remote read from AP LAPIC_MSG_REG about max fid.
Then calculate the common max fid that can be used for all
APs and BSP */
ap_apicidx.num = 0;
- for_each_ap(bsp_apicid, SET_FIDVID_CORE_RANGE, store_ap_apicid,
&ap_apicidx);
+ for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, store_ap_apicid,
&ap_apicidx);
for (i = 0; i < ap_apicidx.num; i++) {
init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
}
#else
- for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1,
&fv);
+ for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY,
init_fidvid_bsp_stage1, &fv);
#endif
print_debug_fv("common_fid = ", fv.common_fid);
Index: src/cpu/amd/model_10xxx/init_cpus.c
===================================================================
--- src/cpu/amd/model_10xxx/init_cpus.c (Revision 6029)
+++ src/cpu/amd/model_10xxx/init_cpus.c (Arbeitskopie)
@@ -28,17 +28,6 @@
#include <cpu/x86/mtrr/earlymtrr.c>
#include <northbridge/amd/amdfam10/raminit_amdmct.c>
-//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and
CONFIG_LIFT_BSP_APIC_ID
-#ifndef SET_FIDVID
- #define SET_FIDVID 1
-#endif
-
-#ifndef SET_FIDVID_CORE0_ONLY
- /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores,
- Need to do every AP to set common FID/VID */
- #define SET_FIDVID_CORE0_ONLY 0
-#endif
-
static void prep_fid_change(void);
static void init_fidvid_stage2(u32 apicid, u32 nodeid);
void cpuSetAMDMSR(void);
@@ -166,7 +155,7 @@
return result;
}
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid);
#endif
@@ -338,8 +327,8 @@
update_microcode(cpuid_eax(1));
cpuSetAMDMSR();
-#if SET_FIDVID == 1
-#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1)
+#if CONFIG_SET_FIDVID
+#if (CONFIG_LOGICAL_CPUS == 1) && CONFIG_SET_FIDVID_CORE0_ONLY
// Run on all AP for proper FID/VID setup.
if (id.coreid == 0) // only need set fid for core0
#endif
@@ -928,7 +917,7 @@
cpuSetAMDPCI(i);
}
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
// Prep each node for FID/VID setup.
prep_fid_change();
#endif
Index: src/mainboard/iwill/dk8_htx/romstage.c
===================================================================
--- src/mainboard/iwill/dk8_htx/romstage.c (Revision 6029)
+++ src/mainboard/iwill/dk8_htx/romstage.c (Arbeitskopie)
@@ -3,11 +3,6 @@
//used by incoherent_ht
//#define K8_ALLOCATE_IO_RANGE 1
-//used by init_cpus and fidvid
-#define SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -174,7 +169,7 @@
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes,
sbdn
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
{
msr_t msr;
Index: src/mainboard/iwill/dk8s2/romstage.c
===================================================================
--- src/mainboard/iwill/dk8s2/romstage.c (Revision 6029)
+++ src/mainboard/iwill/dk8s2/romstage.c (Arbeitskopie)
@@ -3,11 +3,6 @@
//used by incoherent_ht
//#define K8_ALLOCATE_IO_RANGE 1
-//used by init_cpus and fidvid
-#define SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -174,7 +169,7 @@
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes,
sbdn
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
{
msr_t msr;
Index: src/mainboard/iwill/dk8x/romstage.c
===================================================================
--- src/mainboard/iwill/dk8x/romstage.c (Revision 6029)
+++ src/mainboard/iwill/dk8x/romstage.c (Arbeitskopie)
@@ -3,11 +3,6 @@
//used by incoherent_ht
//#define K8_ALLOCATE_IO_RANGE 1
-//used by init_cpus and fidvid
-#define SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -174,7 +169,7 @@
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes,
sbdn
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
{
msr_t msr;
Index: src/mainboard/asrock/939a785gmh/Kconfig
===================================================================
--- src/mainboard/asrock/939a785gmh/Kconfig (Revision 6029)
+++ src/mainboard/asrock/939a785gmh/Kconfig (Arbeitskopie)
@@ -25,6 +25,7 @@
select GFXUMA
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/asrock/939a785gmh/romstage.c
===================================================================
--- src/mainboard/asrock/939a785gmh/romstage.c (Revision 6029)
+++ src/mainboard/asrock/939a785gmh/romstage.c (Arbeitskopie)
@@ -18,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define SET_FIDVID 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
Index: src/mainboard/supermicro/h8dmr/Kconfig
===================================================================
--- src/mainboard/supermicro/h8dmr/Kconfig (Revision 6029)
+++ src/mainboard/supermicro/h8dmr/Kconfig (Arbeitskopie)
@@ -22,6 +22,7 @@
select BOARD_ROMSIZE_KB_1024
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/supermicro/h8dmr/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dmr/romstage.c (Revision 6029)
+++ src/mainboard/supermicro/h8dmr/romstage.c (Arbeitskopie)
@@ -26,11 +26,6 @@
#define SET_NB_CFG_54 1
#endif
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -201,7 +196,7 @@
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes,
sbdn
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
Index: src/mainboard/supermicro/h8dme/Kconfig
===================================================================
--- src/mainboard/supermicro/h8dme/Kconfig (Revision 6029)
+++ src/mainboard/supermicro/h8dme/Kconfig (Arbeitskopie)
@@ -23,6 +23,7 @@
select BOARD_ROMSIZE_KB_1024
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/supermicro/h8dme/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dme/romstage.c (Revision 6029)
+++ src/mainboard/supermicro/h8dme/romstage.c (Arbeitskopie)
@@ -23,11 +23,6 @@
#define SET_NB_CFG_54 1
#endif
-// used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -272,7 +267,7 @@
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn,
nodes, sbdn
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
{
msr_t msr;
Index: src/mainboard/supermicro/h8dmr_fam10/romstage.c
===================================================================
--- src/mainboard/supermicro/h8dmr_fam10/romstage.c (Revision 6029)
+++ src/mainboard/supermicro/h8dmr_fam10/romstage.c (Arbeitskopie)
@@ -27,9 +27,6 @@
#define SET_NB_CFG_54 1
#endif
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -214,7 +211,7 @@
post_code(0x38);
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
msr.hi, msr.lo);
Index: src/mainboard/supermicro/h8qme_fam10/romstage.c
===================================================================
--- src/mainboard/supermicro/h8qme_fam10/romstage.c (Revision 6029)
+++ src/mainboard/supermicro/h8qme_fam10/romstage.c (Arbeitskopie)
@@ -27,9 +27,6 @@
#define SET_NB_CFG_54 1
#endif
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -256,7 +253,7 @@
post_code(0x38);
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi,
msr.lo);
Index: src/mainboard/kontron/kt690/Kconfig
===================================================================
--- src/mainboard/kontron/kt690/Kconfig (Revision 6029)
+++ src/mainboard/kontron/kt690/Kconfig (Arbeitskopie)
@@ -23,6 +23,7 @@
select RAMINIT_SYSINFO
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/kontron/kt690/romstage.c
===================================================================
--- src/mainboard/kontron/kt690/romstage.c (Revision 6029)
+++ src/mainboard/kontron/kt690/romstage.c (Arbeitskopie)
@@ -18,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define SET_FIDVID 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
Index: src/mainboard/gigabyte/m57sli/Kconfig
===================================================================
--- src/mainboard/gigabyte/m57sli/Kconfig (Revision 6029)
+++ src/mainboard/gigabyte/m57sli/Kconfig (Arbeitskopie)
@@ -24,6 +24,7 @@
select BOARD_ROMSIZE_KB_512
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/gigabyte/m57sli/romstage.c
===================================================================
--- src/mainboard/gigabyte/m57sli/romstage.c (Revision 6029)
+++ src/mainboard/gigabyte/m57sli/romstage.c (Arbeitskopie)
@@ -26,11 +26,6 @@
#define SET_NB_CFG_54 1
#endif
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -226,7 +221,7 @@
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes,
sbdn
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
{
msr_t msr;
Index: src/mainboard/gigabyte/ma78gm/romstage.c
===================================================================
--- src/mainboard/gigabyte/ma78gm/romstage.c (Revision 6029)
+++ src/mainboard/gigabyte/ma78gm/romstage.c (Arbeitskopie)
@@ -27,10 +27,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -195,7 +191,7 @@
rs780_early_setup();
sb700_early_setup();
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
msr.hi, msr.lo);
Index: src/mainboard/gigabyte/ga_2761gxdk/Kconfig
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/Kconfig (Revision 6029)
+++ src/mainboard/gigabyte/ga_2761gxdk/Kconfig (Arbeitskopie)
@@ -20,6 +20,7 @@
select BOARD_ROMSIZE_KB_512
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/gigabyte/ga_2761gxdk/romstage.c
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/romstage.c (Revision 6029)
+++ src/mainboard/gigabyte/ga_2761gxdk/romstage.c (Arbeitskopie)
@@ -28,11 +28,6 @@
#define SET_NB_CFG_54 1
#endif
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -215,7 +210,7 @@
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes,
sbdn
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
{
msr_t msr;
Index: src/mainboard/gigabyte/ma785gmt/romstage.c
===================================================================
--- src/mainboard/gigabyte/ma785gmt/romstage.c (Revision 6029)
+++ src/mainboard/gigabyte/ma785gmt/romstage.c (Arbeitskopie)
@@ -23,10 +23,6 @@
#define SET_NB_CFG_54 1
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -192,7 +188,7 @@
rs780_early_setup();
sb700_early_setup();
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
msr.hi, msr.lo);
Index: src/mainboard/amd/mahogany/Kconfig
===================================================================
--- src/mainboard/amd/mahogany/Kconfig (Revision 6029)
+++ src/mainboard/amd/mahogany/Kconfig (Arbeitskopie)
@@ -25,6 +25,7 @@
select RAMINIT_SYSINFO
select GFXUMA
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/amd/mahogany/romstage.c
===================================================================
--- src/mainboard/amd/mahogany/romstage.c (Revision 6029)
+++ src/mainboard/amd/mahogany/romstage.c (Arbeitskopie)
@@ -17,7 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define SET_FIDVID 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
Index: src/mainboard/amd/pistachio/Kconfig
===================================================================
--- src/mainboard/amd/pistachio/Kconfig (Revision 6029)
+++ src/mainboard/amd/pistachio/Kconfig (Arbeitskopie)
@@ -22,6 +22,7 @@
select BOARD_ROMSIZE_KB_1024
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/amd/pistachio/romstage.c
===================================================================
--- src/mainboard/amd/pistachio/romstage.c (Revision 6029)
+++ src/mainboard/amd/pistachio/romstage.c (Arbeitskopie)
@@ -17,7 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define SET_FIDVID 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
Index: src/mainboard/amd/dbm690t/Kconfig
===================================================================
--- src/mainboard/amd/dbm690t/Kconfig (Revision 6029)
+++ src/mainboard/amd/dbm690t/Kconfig (Arbeitskopie)
@@ -22,6 +22,7 @@
select BOARD_ROMSIZE_KB_1024
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/amd/dbm690t/romstage.c
===================================================================
--- src/mainboard/amd/dbm690t/romstage.c (Revision 6029)
+++ src/mainboard/amd/dbm690t/romstage.c (Arbeitskopie)
@@ -17,7 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define SET_FIDVID 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
Index: src/mainboard/amd/serengeti_cheetah/romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/romstage.c (Revision 6029)
+++ src/mainboard/amd/serengeti_cheetah/romstage.c (Arbeitskopie)
@@ -3,11 +3,6 @@
//used by incoherent_ht
//#define K8_ALLOCATE_IO_RANGE 1
-//used by init_cpus and fidvid
-#define SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -153,7 +148,7 @@
int needs_reset;
unsigned bsp_apicid = 0;
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
struct cpuid_result cpuid1;
#endif
@@ -217,7 +212,7 @@
needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
Index: src/mainboard/amd/mahogany_fam10/romstage.c
===================================================================
--- src/mainboard/amd/mahogany_fam10/romstage.c (Revision 6029)
+++ src/mainboard/amd/mahogany_fam10/romstage.c (Arbeitskopie)
@@ -27,10 +27,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -196,7 +192,7 @@
rs780_early_setup();
sb700_early_setup();
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
msr.hi, msr.lo);
Index: src/mainboard/amd/tilapia_fam10/romstage.c
===================================================================
--- src/mainboard/amd/tilapia_fam10/romstage.c (Revision 6029)
+++ src/mainboard/amd/tilapia_fam10/romstage.c (Arbeitskopie)
@@ -27,10 +27,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -196,7 +192,7 @@
rs780_early_setup();
sb700_early_setup();
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
msr.hi, msr.lo);
Index: src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c (Revision 6029)
+++ src/mainboard/amd/serengeti_cheetah_fam10/romstage.c (Arbeitskopie)
@@ -27,10 +27,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -195,7 +191,7 @@
post_code(0x38);
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
msr.hi, msr.lo);
Index: src/mainboard/iei/kino-780am2-fam10/romstage.c
===================================================================
--- src/mainboard/iei/kino-780am2-fam10/romstage.c (Revision 6029)
+++ src/mainboard/iei/kino-780am2-fam10/romstage.c (Arbeitskopie)
@@ -29,10 +29,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
/* UART address and device number */
#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
@@ -201,7 +197,7 @@
rs780_early_setup();
sb700_early_setup();
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
msr.hi, msr.lo);
Index: src/mainboard/hp/dl145_g3/Kconfig
===================================================================
--- src/mainboard/hp/dl145_g3/Kconfig (Revision 6029)
+++ src/mainboard/hp/dl145_g3/Kconfig (Arbeitskopie)
@@ -22,6 +22,7 @@
select RAMINIT_SYSINFO
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/hp/dl145_g3/romstage.c
===================================================================
--- src/mainboard/hp/dl145_g3/romstage.c (Revision 6029)
+++ src/mainboard/hp/dl145_g3/romstage.c (Arbeitskopie)
@@ -32,11 +32,6 @@
#define SET_NB_CFG_54 1
#endif
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -232,7 +227,7 @@
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes,
sbdn
bcm5785_early_setup();
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
Index: src/mainboard/hp/dl165_g6_fam10/romstage.c
===================================================================
--- src/mainboard/hp/dl165_g6_fam10/romstage.c (Revision 6029)
+++ src/mainboard/hp/dl165_g6_fam10/romstage.c (Arbeitskopie)
@@ -33,9 +33,6 @@
#define SET_NB_CFG_54 1
#endif
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -187,7 +184,7 @@
wait_all_other_cores_started(bsp_apicid);
#endif
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n",
msr.hi, msr.lo);
Index: src/mainboard/tyan/s2912/romstage.c
===================================================================
--- src/mainboard/tyan/s2912/romstage.c (Revision 6029)
+++ src/mainboard/tyan/s2912/romstage.c (Arbeitskopie)
@@ -26,11 +26,6 @@
#define SET_NB_CFG_54 1
#endif
-//used by init_cpus and fidvid
-#define SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -208,7 +203,7 @@
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes,
sbdn
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
{
msr_t msr;
Index: src/mainboard/tyan/s2912_fam10/romstage.c
===================================================================
--- src/mainboard/tyan/s2912_fam10/romstage.c (Revision 6029)
+++ src/mainboard/tyan/s2912_fam10/romstage.c (Arbeitskopie)
@@ -27,9 +27,6 @@
#define SET_NB_CFG_54 1
#endif
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -216,7 +213,7 @@
post_code(0x38);
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n",
msr.hi, msr.lo);
Index: src/mainboard/msi/ms9282/romstage.c
===================================================================
--- src/mainboard/msi/ms9282/romstage.c (Revision 6029)
+++ src/mainboard/msi/ms9282/romstage.c (Arbeitskopie)
@@ -24,12 +24,6 @@
#define SET_NB_CFG_54 1
-// used by init_cpus and fidvid (disabled until someone tests this)
-// #define SET_FIDVID 1
-#define SET_FIDVID 0
-// if we want to wait for core1 done before DQS training, set it to 0
-// #define SET_FIDVID_CORE0_ONLY 1
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
Index: src/mainboard/msi/ms9185/Kconfig
===================================================================
--- src/mainboard/msi/ms9185/Kconfig (Revision 6029)
+++ src/mainboard/msi/ms9185/Kconfig (Arbeitskopie)
@@ -22,6 +22,7 @@
select RAMINIT_SYSINFO
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/msi/ms9185/romstage.c
===================================================================
--- src/mainboard/msi/ms9185/romstage.c (Revision 6029)
+++ src/mainboard/msi/ms9185/romstage.c (Arbeitskopie)
@@ -28,11 +28,6 @@
//used by incoherent_ht
//#define K8_ALLOCATE_IO_RANGE 1
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -204,7 +199,7 @@
needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
{
msr_t msr;
Index: src/mainboard/msi/ms9652_fam10/romstage.c
===================================================================
--- src/mainboard/msi/ms9652_fam10/romstage.c (Revision 6029)
+++ src/mainboard/msi/ms9652_fam10/romstage.c (Arbeitskopie)
@@ -27,9 +27,6 @@
#define SET_NB_CFG_54 1
#endif
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -224,7 +221,7 @@
post_code(0x38);
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n",
msr.hi, msr.lo);
Index: src/mainboard/msi/ms7260/Kconfig
===================================================================
--- src/mainboard/msi/ms7260/Kconfig (Revision 6029)
+++ src/mainboard/msi/ms7260/Kconfig (Arbeitskopie)
@@ -22,6 +22,7 @@
select BOARD_ROMSIZE_KB_512
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/msi/ms7260/romstage.c
===================================================================
--- src/mainboard/msi/ms7260/romstage.c (Revision 6029)
+++ src/mainboard/msi/ms7260/romstage.c (Arbeitskopie)
@@ -29,12 +29,6 @@
#define SET_NB_CFG_54 1
#endif
-/* Used by init_cpus and fidvid. */
-#define SET_FIDVID 1
-
-/* If we want to wait for core1 done before DQS training, set it to 0. */
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -202,7 +196,7 @@
/* Set up chains and store link pair for optimization later. */
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
{
msr_t msr = rdmsr(0xc0010042);
print_debug("begin msr fid, vid ");
Index: src/mainboard/jetway/pa78vm5/romstage.c
===================================================================
--- src/mainboard/jetway/pa78vm5/romstage.c (Revision 6029)
+++ src/mainboard/jetway/pa78vm5/romstage.c (Arbeitskopie)
@@ -28,10 +28,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -204,7 +200,7 @@
rs780_early_setup();
sb700_early_setup();
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
msr.hi, msr.lo);
Index: src/mainboard/technexion/tim8690/Kconfig
===================================================================
--- src/mainboard/technexion/tim8690/Kconfig (Revision 6029)
+++ src/mainboard/technexion/tim8690/Kconfig (Arbeitskopie)
@@ -22,6 +22,7 @@
select BOARD_ROMSIZE_KB_512
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/technexion/tim8690/romstage.c
===================================================================
--- src/mainboard/technexion/tim8690/romstage.c (Revision 6029)
+++ src/mainboard/technexion/tim8690/romstage.c (Arbeitskopie)
@@ -17,7 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define SET_FIDVID 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
Index: src/mainboard/technexion/tim5690/Kconfig
===================================================================
--- src/mainboard/technexion/tim5690/Kconfig (Revision 6029)
+++ src/mainboard/technexion/tim5690/Kconfig (Arbeitskopie)
@@ -23,6 +23,7 @@
select BOARD_ROMSIZE_KB_512
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/technexion/tim5690/romstage.c
===================================================================
--- src/mainboard/technexion/tim5690/romstage.c (Revision 6029)
+++ src/mainboard/technexion/tim5690/romstage.c (Arbeitskopie)
@@ -17,7 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define SET_FIDVID 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif
Index: src/mainboard/nvidia/l1_2pvv/romstage.c
===================================================================
--- src/mainboard/nvidia/l1_2pvv/romstage.c (Revision 6029)
+++ src/mainboard/nvidia/l1_2pvv/romstage.c (Arbeitskopie)
@@ -26,11 +26,6 @@
#define SET_NB_CFG_54 1
#endif
-//used by init_cpus and fidvid
-#define SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -213,7 +208,7 @@
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes,
sbdn
-#if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
{
msr_t msr;
Index: src/mainboard/asus/m4a785-m/romstage.c
===================================================================
--- src/mainboard/asus/m4a785-m/romstage.c (Revision 6029)
+++ src/mainboard/asus/m4a785-m/romstage.c (Arbeitskopie)
@@ -27,10 +27,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -197,7 +193,7 @@
rs780_early_setup();
sb700_early_setup();
- #if SET_FIDVID == 1
+ #if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
msr.hi, msr.lo);
Index: src/mainboard/asus/a8v-e_se/Kconfig
===================================================================
--- src/mainboard/asus/a8v-e_se/Kconfig (Revision 6029)
+++ src/mainboard/asus/a8v-e_se/Kconfig (Arbeitskopie)
@@ -17,6 +17,7 @@
select BOARD_ROMSIZE_KB_512
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/asus/a8v-e_se/romstage.c
===================================================================
--- src/mainboard/asus/a8v-e_se/romstage.c (Revision 6029)
+++ src/mainboard/asus/a8v-e_se/romstage.c (Arbeitskopie)
@@ -24,12 +24,6 @@
unsigned int get_sbdn(unsigned bus);
-/* Used by init_cpus and fidvid */
-#define SET_FIDVID 1
-
-/* If we want to wait for core1 done before DQS training, set it to 0. */
-#define SET_FIDVID_CORE0_ONLY 1
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
Index: src/mainboard/asus/m2v-mx_se/Kconfig
===================================================================
--- src/mainboard/asus/m2v-mx_se/Kconfig (Revision 6029)
+++ src/mainboard/asus/m2v-mx_se/Kconfig (Arbeitskopie)
@@ -37,6 +37,7 @@
select TINY_BOOTBLOCK
select HAVE_MAINBOARD_RESOURCES
select QRANK_DIMM_SUPPORT
+ select SET_FIDVID
config MAINBOARD_DIR
string
Index: src/mainboard/asus/m2v-mx_se/romstage.c
===================================================================
--- src/mainboard/asus/m2v-mx_se/romstage.c (Revision 6029)
+++ src/mainboard/asus/m2v-mx_se/romstage.c (Arbeitskopie)
@@ -24,12 +24,6 @@
unsigned int get_sbdn(unsigned bus);
-/* Used by init_cpus and fidvid */
-#define SET_FIDVID 1
-
-/* If we want to wait for core1 done before DQS training, set it to 0. */
-#define SET_FIDVID_CORE0_ONLY 1
-
#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
