This fixes a FIXME in src/cpu/amd/mtrr/amd_mtrr.c and shuts up the Linux kernel, which was previously complaining that the MTRR setup is wrong, if the cpu supports more than CONFIG_CPU_ADDR_BITS bits of address space.
dmesg without patch: |MTRR variable ranges enabled: | 0 base 0000000000 mask 0F00000000 write-back | 1 base 0100000000 mask 0FC0000000 write-back | 2 base 00E0000000 mask 0FE0000000 uncachable | 3 disabled | 4 disabled | 5 disabled | 6 disabled | 7 disabled |mtrr: your BIOS has configured an incorrect mask, fixing it. dmesg with patch: |MTRR variable ranges enabled: | 0 base 0000000000 mask FF00000000 write-back | 1 base 0100000000 mask FFC0000000 write-back | 2 base 00E0000000 mask FFE0000000 uncachable | 3 disabled | 4 disabled | 5 disabled | 6 disabled | 7 disabled Shamelessly copied from Linux arch/x86/kernel/cpu/mtrr/main.c Signed-off-by: Tobias Diedrich <[email protected]> --- Index: src/cpu/amd/mtrr/amd_mtrr.c =================================================================== --- src/cpu/amd/mtrr/amd_mtrr.c (revision 5985) +++ src/cpu/amd/mtrr/amd_mtrr.c (working copy) @@ -1,5 +1,6 @@ #include <console/console.h> #include <device/device.h> +#include <arch/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> @@ -175,11 +176,13 @@ enable_cache(); - /* FIXME we should probably query the cpu for this - * but so far this is all any recent AMD cpu has supported. - */ address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48 + /* AMD specific MSR to query number of address bits */ + if (cpuid_eax(0x80000000) >= 0x80000008) { + address_bits = cpuid_eax(0x80000008) & 0xff; + } + /* Now that I have mapped what is memory and what is not * Setup the mtrrs so we can cache the memory. */ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
