-----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Tobias Diedrich Sent: Sunday, November 07, 2010 06:47 AM To: [email protected] Cc: Rudolf Marek; Tobias Diedrich Subject: [coreboot] [patch 16/16] Ranges unavailable for PCI BARs should bemarked as reserved in the E820 memory map,in case the OS wants to change the BARs.
]Linux also needs the MMCONF area to be reserved either in E820 or ]as an ACPI motherboard resource or it will not enable MMCONFIG ]and the extended pcie configuration area will be unaccessible: ] ]This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF ]resource flags to do this. ]I also added a new resource for the mapped bios rom area just below 4GB. ]I'm not sure if the choice for the index parameter of new_resource() ]is correct though. ]Note that the bios rom decode is enabled in ]src/southbridge/via/vt8237r/vt8237r_early_smbus.c ]for the whole 4MB area (even though the comment says 1MB). Thank you Tobias. To be even more conservative, the upper 5 MB of the first 4GB can be reserved for flash memory. This is because many LPC flash chips place the jedec ID register of the boot device at address ffbc0000. Thanks, Scott -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
