Author: ranma Date: Wed Nov 24 20:57:08 2010 New Revision: 6121 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6121
Log: With low serial console loglevels a pcie graphics card is not initialized properly because the pcie link takes some time to come up. I set the timeout rather arbitrary to 100ms, this is what a BIOS_ERR and higher only boot looks like on my system (with pcie printks set to BIOS_ERR so they show up): |Device error |Device error |PCI: 00:02.0 PCIe link up after 35800 us |PCI: 00:03.0 PCIe link up after 12900 us |PCI: 00:03.1 PCIe link timeout |PCI: 00:03.2 PCIe link up after 32000 us |APIC: 00 missing read_resources |I2C: 01:50 missing read_resources |I2C: 01:51 missing read_resources |I2C: 01:52 missing read_resources |I2C: 01:53 missing read_resources |Start bios (version pre-0.6.2-20101025_023503-nukunuku) Signed-off-by: Tobias Diedrich <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/src/southbridge/via/k8t890/k8t890_pcie.c Modified: trunk/src/southbridge/via/k8t890/k8t890_pcie.c ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890_pcie.c Wed Nov 24 01:39:44 2010 (r6120) +++ trunk/src/southbridge/via/k8t890/k8t890_pcie.c Wed Nov 24 20:57:08 2010 (r6121) @@ -22,6 +22,7 @@ #include <device/pci.h> #include <device/pciexp.h> #include <device/pci_ids.h> +#include <delay.h> #include "k8t890.h" /* @@ -30,16 +31,10 @@ * http://linux.via.com.tw/ */ -static void peg_init(struct device *dev) +static void pcie_common_init(struct device *dev) { u8 reg; - - printk(BIOS_DEBUG, "Configuring PCIe PEG\n"); - dump_south(dev); - - /* Disable link. */ - reg = pci_read_config8(dev, 0x50); - pci_write_config8(dev, 0x50, reg | 0x10); + int i, up; /* Disable downstream read cycle retry, * otherwise the bus scan will hang if no device is plugged in. */ @@ -60,14 +55,48 @@ */ pci_write_config8(dev, 0xe1, 0xb); + /* Set replay timer limit. */ + pci_write_config8(dev, 0xb1, 0xf0); + + /* Enable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg & ~0x10); + + /* Wait up to 100ms for link to come up */ + up = 0; + for (i=0; i<1000; i++) { + if (pci_read_config16(dev, 0x52) & (1<<13)) { + up = 1; + break; + } + udelay(100); + } + + printk(BIOS_SPEW, "%s PCIe link ", dev_path(dev)); + if (up) + printk(BIOS_SPEW, "up after %d us\n", i*100); + else + printk(BIOS_SPEW, "timeout\n"); + + dump_south(dev); +} + +static void peg_init(struct device *dev) +{ + u8 reg; + + printk(BIOS_DEBUG, "Configuring PCIe PEG\n"); + dump_south(dev); + + /* Disable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x10); + /* * pci_write_config8(dev, 0xe2, 0x0); * pci_write_config8(dev, 0xe3, 0x92); */ - /* Set replay timer limit. */ - pci_write_config8(dev, 0xb1, 0xf0); - /* Bit0 = 1 SDP (Start DLLP) always at Lane0. */ reg = pci_read_config8(dev, 0xb8); pci_write_config8(dev, 0xb8, reg | 0x1); @@ -79,11 +108,7 @@ reg = pci_read_config8(dev, 0xa4); pci_write_config8(dev, 0xa4, reg | 0x30); - /* Enable link. */ - reg = pci_read_config8(dev, 0x50); - pci_write_config8(dev, 0x50, reg & ~0x10); - - dump_south(dev); + pcie_common_init(dev); } static void pcie_init(struct device *dev) @@ -97,33 +122,7 @@ reg = pci_read_config8(dev, 0x50); pci_write_config8(dev, 0x50, reg | 0x10); - /* Disable downstream read cycle retry, - * otherwise the bus scan will hang if no device is plugged in. */ - reg = pci_read_config8(dev, 0xa3); - pci_write_config8(dev, 0xa3, reg & ~0x01); - - /* Use PHY negotiation for lane config */ - reg = pci_read_config8(dev, 0xc1); - pci_write_config8(dev, 0xc1, reg & ~0x1f); - - /* Award has 0xb, VIA recommends 0xd, default 0x8. - * bit4: receive polarity change control - * bits3:2: squelch window select 64~175mv - * bit1: Number of non-idle bits detected before exiting idle state - * 0: 10 bits, 1: 2 bits - * bit0: Number of idle bits detected before entering idle state - * 0: 10 bits, 1: 2 bits - */ - pci_write_config8(dev, 0xe1, 0xb); - - /* Set replay timer limit. */ - pci_write_config8(dev, 0xb1, 0xf0); - - /* Enable link. */ - reg = pci_read_config8(dev, 0x50); - pci_write_config8(dev, 0x50, reg & ~0x10); - - dump_south(dev); + pcie_common_init(dev); } static const struct device_operations peg_ops = { -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
