Author: ranma Date: Wed Nov 24 21:03:09 2010 New Revision: 6122 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6122
Log: S3 support for ASUS M2V This adds the board-specific parts for S3 support on the M2V board. Signed-off-by: Tobias Diedrich <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/src/mainboard/asus/m2v/Kconfig trunk/src/mainboard/asus/m2v/dsdt.asl trunk/src/mainboard/asus/m2v/romstage.c Modified: trunk/src/mainboard/asus/m2v/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m2v/Kconfig Wed Nov 24 20:57:08 2010 (r6121) +++ trunk/src/mainboard/asus/m2v/Kconfig Wed Nov 24 21:03:09 2010 (r6122) @@ -17,6 +17,7 @@ select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select TINY_BOOTBLOCK + select HAVE_ACPI_RESUME select HAVE_PIRQ_TABLE select PIRQ_ROUTE select HAVE_ACPI_TABLES Modified: trunk/src/mainboard/asus/m2v/dsdt.asl ============================================================================== --- trunk/src/mainboard/asus/m2v/dsdt.asl Wed Nov 24 20:57:08 2010 (r6121) +++ trunk/src/mainboard/asus/m2v/dsdt.asl Wed Nov 24 21:03:09 2010 (r6122) @@ -59,10 +59,10 @@ /* _PR CPU0 is dynamically supplied by SSDT */ - /* For now only define 2 power states: + /* We define 3 power states: * - S0 which is fully on + * - S3 which is suspend to ram * - S5 which is soft off - * Any others would involve declaring the wake up methods. * * Package contents: * ofs len desc @@ -73,6 +73,7 @@ * 2 2 Reserved */ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S3, Package () { 0x01, 0x01, 0x00, 0x00 }) Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) /* Root of the bus hierarchy */ @@ -341,6 +342,7 @@ Device (SBRG) { /* southbridge */ Name (_ADR, 0x00110000) + OperationRegion (PCIC, PCI_Config, 0x0, 0x100) /* PS/2 keyboard (seems to be important for WinXP install) */ Device (KBD) @@ -459,9 +461,9 @@ } } - OperationRegion (PCI0.SBRG.SBR1, PCI_Config, 0x55, 0x03) - Field (PCI0.SBRG.SBR1, ByteAcc, NoLock, Preserve) + Field (PCI0.SBRG.PCIC, ByteAcc, NoLock, Preserve) { + Offset (0x55), /* * Offset 0x55: * 3-0: reserved @@ -538,4 +540,25 @@ PCI_INTX_DEV(INTC, PINC, 3) PCI_INTX_DEV(INTD, PIND, 4) } + + Field (_SB.PCI0.SBRG.PCIC, ByteAcc, NoLock, Preserve) + { + Offset (0x94), + /* two LSB bits are blink rate */ + LEDR, 2, + } + + Method (_PTS, 1, NotSerialized) + { + /* blink power led while suspended */ + Store (0x1, LEDR) + } + + Method (_WAK, 1, NotSerialized) + { + /* stop power led blinking */ + Store (0x0, LEDR) + /* wake OK */ + Return(Package(0x02){0x00, 0x00}) + } } Modified: trunk/src/mainboard/asus/m2v/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v/romstage.c Wed Nov 24 20:57:08 2010 (r6121) +++ trunk/src/mainboard/asus/m2v/romstage.c Wed Nov 24 21:03:09 2010 (r6122) @@ -73,6 +73,15 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" + +// Now, this needs to be included because it relies on the symbol +// __PRE_RAM__ being set during CAR stage (in order to compile the +// BSS free versions of the functions). Either rewrite the code +// to be always BSS free, or invent a flag that's better suited than +// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) +// +#include "lib/cbmem.c" + #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/resourcemap.c" @@ -242,6 +251,7 @@ enable_rom_decode(); m2v_bus_init(); m2v_it8712f_gpio_init(); + it8712f_enable_3vsbsw(); printk(BIOS_INFO, "now booting... \n"); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
